LTC3589 datasheet(22/36 Pages) LINER

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LTC3375

3375fa

For more information www.linear.com/3375

operaTion

the write address is 68h and the read address is 69h. The

LTC3375 will acknowledge both its read and write address.

I2C Sub-Addressed Writing

The LTC3375 has 13 command registers for control input.

They are accessed by the I2C port via a sub-addressed

writing system.

AsinglewritecycleoftheLTC3375consistsofexactlythree

bytes except when a clear interrupt command is written.

The first byte is always the LTC3375’s write address. The

second byte represents the LTC3375’s sub-address. The

sub-address is a pointer which directs the subsequent

data byte within the LTC3375. The third byte consists of

the data to be written to the location pointed to by the

sub-address. The LTC3375 contains 12 control registers

which can be written to.

I2C Bus Write Operation

The master initiates communication with the LTC3375

with a START condition and the LTC3375’s write address.

If the address matches that of the LTC3375, the LTC3375

returns an acknowledge. The master should then deliver

the sub-address. Again the LTC3375 acknowledges and

the cycle is repeated for the data byte. The data byte is

transferred to an internal holding latch upon the return

of its acknowledge by the LTC3375. This procedure must

be repeated for each sub-address that requires new data.

After one or more cycles of [ADDRESS][SUB-ADDRESS]

[DATA], the master may terminate the communication

with a STOP condition. Multiple sub-addresses may

be written to with a single address command using a

[ADDRESS][SUB-ADDRESS][DATA][SUB-ADDRESS]

[DATA] sequence. Alternatively, a REPEAT-START condi-

tion can be initiated by the master and another chip on

the I2C bus can be addressed. This cycle can continue

indefinitely and the LTC3375 will remember the last input

valid data that it received. Once all chips on the bus have

been addressed and sent valid data, a global STOP can

be sent and the LTC3375 will update its command latches

with the data that it had received.

It is important to understand that until a STOP signal is

transmitted, data written to the LTC3375 command reg-

isters is not acted on by the LTC3375. Only once a STOP

signal is issued is the data transferred to the command

latch and acted on.

I2C Bus Read Operation

The LTC3375 has 13 command registers and three status

registers.Thecontentsofanyoftheseregisters,exceptfor

the Clear Interrupt (0Fh) register, may be read back via I2C.

To read the data of a register, that register’s sub-address

must be provided to the LTC3375. The bus master reads

the status of the LTC3375 with a START condition followed

by the LTC3375 write address followed by the first data

byte (the sub-address of the register whose data needs

to be read) which is acknowledged by the LTC3375. After

receiving the acknowledge signal from the LTC3375 the

bus master initiates a new START condition followed by

the LTC3375 read address. The LTC3375 acknowledges

the read address and then returns a byte of read back

data from the selected register. A STOP command is not

required for the bus read operation.

Immediately after writing data to a register, the contents

of that register may be read back if the bus master issues

a START condition followed by the LTC3375 read address.

Error Condition Reporting Via RST and IRQ Pins

Error conditions are reported back via the IRQ and RST

pins. After an error condition is detected, status data can

be read back to a microprocessor via I2C to determine the

exact nature of the error condition.

Figure 4 is a simplified schematic showing the signal path

for reporting errors via the RST and IRQ pins.

All buck switching regulators have an internal power good

(PGOOD) signal. When the regulated output voltage of an

enabled switcher rises above 93.5% of its programmed

value, the PGOOD signal will transition high. When the

regulated output voltage falls below 92.5% of its pro-

grammed value, the PGOOD signal is pulled low. If any

internal PGOOD signal is not masked and stays low for

greater than 50µs, then the RST and IRQ pins are pulled

low, indicating to a microprocessor that an error condition

has occurred. The 50µs filter time prevents the pins from

being pulled low due to a transient.

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