LTC3589 datasheet(25/36 Pages) LINER

25 / 36 page

LTC3375

3375fa

For more information www.linear.com/3375

operaTion

After detecting an external clock on the first rising edge of

the SYNC pin, the PLL starts up at the current frequency

being programmed by the RT pin. The internal PLL then

requires a certain number of periods to gradually settle

until the frequency at SW matches the frequency and

phase of SYNC.

When the external clock is removed the LTC3375 needs

approximately 5µs to detect the absence of the external

clock. During this time, the PLL will continue to provide

clock cycles before it recognizes the lack of a SYNC input.

Once the external clock removal has been identified, the

oscillator will gradually adjust its operating frequency to

match the desired frequency programmed at the RT pin.

VCC Shunt Regulator

TheLTC3375hasthecontrolcircuitrytoregulatetheoutput

of an N-type device. The circuit should be connected as

showninFigures6aand6b.ThevoltageatFBVCCwillservo

to 1.20V and VCC can be programmed between 2.7V and

5.5V. The N-type device can be used to regulate a lower

voltage at VCC while being powered from a high voltage

supply. The N-type device must be chosen so that it can

handle the power dissipated in regulating VCC.Theinternal

circuitry of the LTC3375 can only pull-down on the VSHNT

node. A pull-up resistor is required for positive gate drive.

If VCC is incorrectly programmed or a current load at VCC

causes VSHNT to go above 6.1V (typical), then VSHNT will

be internally clamped and VCC may lose regulation.

If the use of the VCC regulator is not desired, then VCC

should be tied to an external DC voltage source and a

decoupling capacitor. FBVCC and VSHNT should be tied

to ground.

Watchdog Timer

Thewatchdogcircuitmonitorsamicroprocessor’sactivity.

The microprocessor is required to change the logic state

of the WDI pin at least once every 1.5 seconds (typical)

in order to clear the watchdog timer and prevent the WDO

pin from signaling a timeout.

The watchdog timer begins running immediately after a

power-on reset. The watchdog timer will continue to run

until a transition is detected on the WDI input. During

this time WDO will be in a Hi-Z state. Once the watchdog

timer times out, WDO will be pulled low and the reset

timer is started. WDO being pulled low may be used to

force a reset on the controlling microprocessor. If no WDI

transition is received when the reset timer times out, after

200ms (typical), WDO will again become Hi-Z and the 1.5

secondswatchdogresettimewillbeginagain.Ifatransition

is received on the WDI input during the watchdog timeout

period, then WDO will become Hi-Z immediately after the

WDI transition and the 1.5 seconds watchdog reset time

will begin at that point.

LTC3589 Datasheet(PDF) 25 Page - Linear Technology

LTC3589 Datasheet(HTML) 25 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL