AD9467 datasheet(24/32 Pages) AD

24 / 32 page

AD9467

Data Sheet

Rev. D | Page 24 of 32

CH1

500mV Ω

CH2

500mV Ω

CH3

500mV Ω

5.0ns/DIV

20.0GS/s

IT 25.0pt/pt

A CH2

10.0V

CLOCK

DCO

DATA

Figure 64. Output Timing Example in LVDS Mode (Default), AD9467-250

An example of the LVDS output using the ANSI-644 standard

(default) data eye and a time interval error (TIE) jitter histogram

with trace lengths of six inches on standard FR-4 material is shown

in Figure 65. It is the responsibility of the user to determine if

the waveforms meet the timing budget of the design.

400

–2

–1

–20

–10

TIME (ns)

300

200

100

–100

–200

–300

–400

TIME (ps)

Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with 6-Inch Trace

Lengths on Standard FR-4, AD9467-250

–40

–20

TIME (ps)

400

–2

–1

TIME (ns)

300

200

100

–100

–200

–300

–400

Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 18-Inch Trace

Lengths on Standard FR-4, AD9467-250

The format of the output data is offset binary by default. An

example of the output coding format can be found in Table 8.

To change the output data format to twos complement or Gray

code, see the Memory Map section.

Table 8. Digital Output Coding

Code

(VIN+) − (VIN−), Input

Span = 2.5 V p-p (V)

Digital Output Offset Binary

(D15:D0)

65,536

+1.25

1111 1111 1111 1111

32,768

0.00

1000 0000 0000 0000

32,767

−0.000038

0111 1111 1111 1111

−1.25

0000 0000 0000 0000

An output clock is provided to assist in capturing data from the

AD9467. Data is clocked out of the AD9467 and must be

captured on the rising and falling edges of the DCO that supports

double data rate (DDR) capturing. See the timing diagram

shown in Figure 2 for more information.

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