Data Sheet

AD9467

Rev. D | Page 25 of 32

There are eight digital output test pattern options available that

can be initiated through the SPI. This is a useful feature when

validating receiver capture and timing. Refer to Table 10 for the

output bit sequencing options available. Some test patterns have

two serial sequential words and can be alternated in various

ways, depending on the test pattern chosen. Note that some

patterns may not adhere to the data format select option.

The PN sequence short pattern produces a pseudorandom bit

tion of the PN sequence and how it is generated can be found

in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only

difference is that the starting value must be a specific value

instead of all 1s (see Table 9 for the initial values).

The PN sequence long pattern produces a pseudorandom bit

description of the PN sequence and how it is generated can be

found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The

only differences are that the starting value must be a specific

value instead of all 1s (see Table 9 for the initial values) and the

AD9467 inverts the bit stream with relation to the ITU standard.

Table 9. PN Sequence

Sequence

Initial

Value

First Three Output

Samples (MSB First)

PN 9 Sequence, Short

0xFFFF

0x87BE, 0xAE64, 0x929D

PN 23 Sequence, Long

0x7FFF

0x7E00, 0x807C, 0x801F

Consult the Memory Map section for information on how to

change these additional digital output timing features through

the SPI.

Overrange (OR) Output Pins

The OR+ and OR− output pins indicate when an applied analog

input is above or below the input full scale of the converter.

If the analog input is in an overrange condition, the OR bit goes

high, coinciding with output data hitting above or below full-

scale. The delay between the time the part actually overranges

and the OR bit going high is the pipeline latency of the part.

SPI Pins: SCLK, SDIO, CSB

For normal SPI operation, these pins should be tied to AGND

through a 100 kΩ resistor on each pin. These pins are both

1.8 V and 3.3 V tolerant. However, the SDIO output logic level

is dependent on the bias of the SPIVDD pin. For 3.3 V output

logic, tie SPIVDD to 3.3 V (AVDD2). For 1.8 V output logic, tie

SPIVDD to 1.8 V (AVDD1).

The CSB pin should be tied to AVDD1 for applications that do

not require SPI mode operation. By tying CSB high, all SCLK

and SDIO information is ignored.

Table 10. Flexible Output Test Modes

Output Test Mode Bit Sequence

Pattern Name

Digital Output Word 1

Digital Output Word 2

Subject to Data

Format Select

0000

Off (default)

N/A1

N/A1

N/A1

0001

Midscale short

1000 0000 0000 0000

Same

Yes

0010

+Full-scale short

1111 1111 1111 1111

Same

Yes

0011

−Full-scale short

0000 0000 0000 0000

Same

Yes

0100

Checkerboard

1010 1010 1010 1010

0101 0101 0101 0101

No

0101

PN sequence long2

N/A1

N/A1

Yes

0110

PN sequence short2

N/A1

N/A1

Yes

0111

One-/zero-word toggle

1111 1111 1111 1111

0000 0000 0000 0000

No

1

N/A = not applicable.

2

All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths to verify data capture to the receiver.