AD9467 datasheet(28/32 Pages) AD

28 / 32 page

AD9467

Data Sheet

Rev. D | Page 28 of 32

MEMORY MAP

READING THE MEMORY MAP TABLE

Each row in the memory map register table (see Table 13) has

eight address locations. The memory map is divided into three

sections: the chip configuration register map (Address 0x00

to Address 0x02), the device index and transfer register map

(Address 0xFF), and the ADC functions register map

(Address 0x08 to Address 0x107).

The leftmost column of the memory map indicates the register

address number, and the default value is shown in the second right-

most column. The (MSB) Bit 7 column is the start of the default

hexadecimal value given. For example, Address 0x2C, the analog

input register, has a default value of 0x00, meaning Bit 7 = 0,

Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and

Bit 0 = 0, or 0000 0000 in binary. This setting is the default for an

ac-coupled analog input condition. By writing a 1 to Bit 2 of this

address, the internal input common-mode buffer is disabled

allowing a dc-coupled input for which the input common mode

voltage can be set externally. For more information on this and

other functions, consult the AN-877 Application Note,

Interfacing to High Speed ADCs via SPI.

RESERVED LOCATIONS

Undefined memory locations should not be written to except

when writing the default values suggested in this data sheet.

Addresses that have values marked as 0 should be considered

reserved and have a 0 written into their registers during power-up.

DEFAULT VALUES

When the AD9467 comes out of a reset, critical registers are

preloaded with default values. These values are indicated in

Table 13, where an X refers to an undefined feature.

LOGIC LEVELS

An explanation of various registers follows: “Bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly, “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Table 13. Memory Map Register1

Addr.

(Hex)

Parameter Name

(MSB)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

(LSB)

Bit 0

Default

Value

(Hex)

Default Notes/

Comments

Chip Configuration Register

chip_port_config

LSB first

1 = on

0 = off

(default)

Soft

reset

1 = on

0 = off

(default)

0x18

The nibbles

should be

mirrored so

that LSB- or

MSB-first mode

is set correctly

regardless of

shift mode.

chip_id

8-Bit Chip ID Bits[7:0]

(AD9467 = 0x50, default)

Read

only

Default is

unique chip ID,

different for

each device.

This is a read-

only register.

chip_grade

Child ID Bits[6:4]

(identify device variants of chip ID)

001 = 200 MSPS

010 = 250 MSPS

Read

only

Child ID used to

differentiate

graded devices.

Device Index and Transfer Register

device_update

transfer

1 = on

0 = off

(default)

0x00

Synchronously

transfers data

from the

master shift

slave.

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