AD9102-EBZ datasheet(35/36 Pages) AD

35 / 36 page

Data Sheet

AD9102

Rev. 0 | Page 35 of 36

Stop Address Register (STOP_ADDR, Address 0x5E)

Table 46. Bit Descriptions for STOP_ADDR

Bits

Bit Name

Settings

Description

Reset

Access

[15:4]

STOP_ADDR

RAM address where DAC stops to read waveform.

0x000

[3:0]

RESERVED

0x0

DDS Cycles Register (DDS_ CYC, Address 0x5F)

Table 47. Bit Descriptions for DDS_CYC

Bits

Bit Name

Settings

Description

Reset

Access

[15:0]

DDS_CYC

Number of sine wave cycles when a DDS prestored waveform with start and

stop delays is selected for the DAC output.

0x0001

Configuration Error Register (CFG_ERROR, Address 0x60)

Table 48. Bit Descriptions for CFG_ERROR

Bits

Bit Name

Settings

Description

Reset

Access

ERROR_CLEAR

Write this bit to clear all errors.

0x0

[14:6]

RESERVED

0x000

DOUT_START_LG_ERR

When the DOUT_START value is larger than the pattern delay,

this error is toggled.

0x0

PAT_DLY_SHORT_ERR

When the pattern delay value is smaller than the default value,

this error is toggled.

0x0

DOUT_START_SHORT_ERR

When the DOUT_START value is smaller than the default value,

this error is toggled.

0x0

PERIOD_SHORT_ERR

When the period register setting value is smaller than the

pattern play cycle, this error is toggled.

0x0

ODD_ADDR_ERR

When the memory pattern play is not of even length in trigger

delay mode, this error flag is toggled.

0x0

MEM_READ_ERR

When there is a memory read conflict, this error flag is toggled.

0x0

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