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AD9102-EBZ Datasheet(PDF) 29 Page - Analog Devices |
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AD9102-EBZ Datasheet(HTML) 29 Page - Analog Devices |
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29 / 36 page  Data Sheet AD9102 Rev. 0 | Page 29 of 36 Clock Control Register (CLOCKCONFIG, Address 0x02) Table 17. Bit Descriptions for CLOCKCONFIG Bits Bit Name Settings Description Reset Access [15:12] RESERVED 0x0 RW 11 DIS_CLK Disable the analog clock to the DAC output of the clock distribution block. 0x0 RW 10 RESERVED 0x0 RW 9 RESERVED Disable the analog clock to the DAC3 output of the clock distribution block. 0x0 RW 8 RESERVED Disable the analog clock to the DAC4 output of the clock distribution block. 0x0 RW 7 DIS_DCLK Disable the clock to core digital block. 0x0 RW 6 CLK_SLEEP Enables a very low power clock mode. 0x0 RW 5 CLK_PDN Disables and powers down the main clock receiver. No clocks are active in the part. 0x0 RW 4 EPS Enable Power Save. This enables a low power option for clock receiver but maintains low jitter performance on the DAC clock rising edge. The DAC clock falling edge is substantially degraded. 0x0 RW 3 DAC_INV_CLK Cannot use EPS while using this bit. Inverts the clock inside DAC Core 1 allowing a 180° phase shift in DAC update timing. 0x0 RW [2:0] RESERVED 0x0 RW Reference Resistor Register (REFADJ, Address 0x03) Table 18. Bit Descriptions for REFADJ Bits Bit Name Settings Description Reset Access [15:6] RESERVED 0x000 RW [5:0] BGDR Adjusts the on-chip REFIO voltage level (see Figure 35). 0x00 RW DAC Analog Gain Register (DACAGAIN, Address 0x07) Table19. Bit Descriptions for DACAGAIN Bits Bit Name Settings Description Reset Access 15 RESERVED 0x0 RW [14:8] DAC_GAIN_CAL DAC analog gain calibration output; read only 0x00 R 7 RESERVED 0x0 RW [6:0] DAC_GAIN DAC analog gain control while not in calibration mode, twos complement 0x00 RW DAC Analog Gain Range Register (DACRANGE, Address 0x08) Table20. Bit Descriptions for DACRANGE Bits Bit Name Settings Description Reset Access [15:2] RESERVED 0x00 RW [1:0] DAC_GAIN_RNG DAC gain range control. 0x0 RW |
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