AD9102-EBZ datasheet(5/36 Pages) AD

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Data Sheet

AD9102

Rev. 0 | Page 5 of 36

DIGITAL TIMING SPECIFICATIONS (1.8 V)

TMIN to TMAX; AVDD = 1.8 V; DVDD = DLDO1 = DLDO2 = 1.8 V; CLKVDD = CLDO = 1.8 V; IOUTFS = 4 mA; maximum sample rate, unless

otherwise noted.

Table 4.

Parameter

Min

Typ

Max

Unit

DAC CLOCK INPUT (CLKIN)

Maximum Clock Rate

180

MSPS

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate (SCLK)

MHz

Minimum Pulse Width High

6.25

Minimum Pulse Width Low

6.25

Setup Time SDIO to SCLK

4.0

Hold Time SDIO to SCLK

5.0

Output Data Valid SCLK to SDO/SDI2/DOUT or SDIO

8.8

Setup Time CS to SCLK

4.0

INPUT/OUTPUT SIGNAL SPECIFICATIONS

Table 5.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

CMOS INPUT LOGIC LEVEL (SCLK, CS, SDIO,

SDO/SDI2/DOUT, RESET, TRIGGER)

Input VIN Logic High

DVDD = 1.8 V

1.53

DVDD = 3.3 V

2.475

Input VIN Logic Low

DVDD = 1.8 V

0.27

DVDD = 3.3 V

0.825

CMOS OUTPUT LOGIC LEVEL (SDIO, SDO/SDI2/DOUT)

Output VOUT Logic High

DVDD = 1.8 V

1.79

DVDD = 3.3 V

3.28

Output VOUT Logic Low

DVDD = 1.8 V

0.25

DVDD = 3.3 V

0.625

DAC CLOCK INPUT (CLKP, CLKN)

Minimum Peak-to-Peak Differential Input Voltage,

VCLKP/VCLKN

150

Maximum Voltage at VCLKP or VCLKN

VDVDD

Minimum Voltage at VCLKP or VCLKN

VDGND

Common-Mode Voltage

Generated on Chip

0.9

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