AD9102-EBZ datasheet(22/36 Pages) AD

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AD9102

Data Sheet

Rev. 0 | Page 22 of 36

PATTERN

STOPS

TRIGGER

CLKP/

CLKN

PATTERN

GENERATOR

STATE

PATTERN ON

PATTERN OFF

tSU

Figure 42. Trigger Rising Edge Initiated Pattern Stop

PATTERN

STOPS

CLKP/

CLKN

RUN

BIT

PATTERN

GENERATOR

STATE

PATTERN ON

PATTERN OFF

Figure 43. RUN Bit Driven Pattern Stop

DAC INPUT DATAPATHS

Timing in the DAC datapaths is governed by the pattern

generator. The datapath includes a waveform selector, a

waveform repeat controller, RAM output and DDS output

multiplier (RAM output can amplitude modulate DDS output),

DDS cycle counter, DAC digital gain multiplier, and a DAC

digital offset summer.

DAC Digital Gain Multiplier

On its way into the DAC, the samples are multiplied by a 12-bit

gain factor that has a range of ±2.0. These gain values are

programmed in the DAC_DGAIN register (Register 0x35).

DAC Digital Offset Summer

DAC input samples are summed with a 12-bit dc offset value.

The dc offset values are programmed in the DACDOF register

(Register 0x25).

DAC Waveform Selectors

Waveform selector inputs are:



Sawtooth generator output



Pseudorandom sequence generator output



DC constant generator output



Pulsed, phase shifted DDS sine wave output



RAM output



Pulsed, phase shifted DDS sine wave output amplitude,

modulated by RAM output

Waveform selection for the DAC is made by programming the

WAV_CONFIG register (Register 0x27).

Pattern Period Repeat Controller

The PATTERN_RPT bit in the PAT_TYPE register (Register

0x1F[0]) controls whether the pattern output auto repeats

(periodic pulse train repeats indefinitely) or repeats a number

of consecutive times defined by the DAC_REPEAT_CYCLE bits

in Register 0x2B. The latter are periodic pulse trains that repeat

a finite number of times.

Number of DDS Cycles

The DAC input datapath establishes the pulse width of the sine

wave output from the DDS in a number of sine wave cycles. The

cycle counts are programmed in the DDS_CYC register.

DDS Phase Shift

The DAC input datapath shifts the phase of the output of the

single common DDS. The phase shift is programmed using the

DDS_PHASE field.

DOUT FUNCTION

In applications where the AD9102 DAC drives a high voltage

amplifier, such as in ultrasound transducer array element driver

signal chains, it can be useful to turn on and off each amplifier

at precise times relative to the waveform generated by the

AD9102 DAC. The SDO/SDI2/DOUT terminal can be

configured to provide this function.

The SPI interface needs to be configured in 3-wire mode

(Figure 30 and Figure 31). This is accomplished by setting the

SPI3WIRE or SPI3WIREM bits in the SPICONFIG register

(Register 0x00). When the SPI_DRV or SPI_DRVM bits of the

SPICONFIG register are set to Logic 1, the SDO/SDI2/DOUT

terminal provides the DOUT function.

Manually Controlled DOUT

If the DOUT_MODE bit = 0 in the DOUT_CONFIG register

(Register 0x2D), DOUT can be turned on or off using the

DOUT_VAL bit of that same register.

Pattern Generator Controlled DOUT

Figure 44 depicts the rising edge of a pattern generator controlled

DOUT pulse. Figure 45 shows the falling edge. A pattern generator

controlled DOUT is set up by setting the DOUT_MODE bit = 1.

Next, the start delay is programmed in the DOUT_START register

(Register 0x2C) and the stop delay is programmed into the

DOUT_STOP bit of the DOUT_CONFIG register.

DOUT goes high when DOUT_START[15:0] CLKP/CLKN

cycles after the falling edge of the signal input to the TRIGGER

pin. DOUT stays high as long as a pattern is being generated.

DOUT goes low when DOUT_STOP[3:0] CLKP/CLKN cycles

after the clock edge that causes pattern generation to stop.

AD9102-EBZ Datasheet(PDF) 22 Page - Analog Devices

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