AD9102-EBZ datasheet(24/36 Pages) AD

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AD9102

Data Sheet

Rev. 0 | Page 24 of 36

PSEUDORANDOM SIGNAL GENERATOR

The pseudorandom noise generator generates a noise signal on

each DAC output when a pseudorandom sequence is selected in

the PRESTORE_SEL fields in the WAV_CONFIG register.

Pseudorandom noise signals are generated as continuous

waveforms only.

DC CONSTANT

A programmable dc current between 0.0 and IOUTFS can be

generated on the DAC when a constant value is selected in the

PRESTORE_SEL bits of the WAV_CONFIG register. DC

constant current is generated as a continuous waveform only.

The dc current level is programmed by writing to the

DAC_CONST field in the appropriate DAC_CST register.

POWER SUPPLY NOTES

The AD9102 supply rails are specified in Table 9. The AD9102

includes three on-chip linear regulators. The supply rails driven by

these regulators are run at 1.8 V. Some usage rules for these

regulators include:

•

When CLKVDD is 2.5 V or higher, the 1.8 V on-chip

CLDO regulator may be used. If CLKVDD = 1.8 V, the

CLDO regulator must be disabled by setting the

PDN_LDO_CLK bit in the POWERCONFIG register.

CLKVDD and CLDO are connected together.

•

When DVDD is 2.5 V or higher, the 1.8 V on-chip DLDO1

and DLDO2 regulators may be used. If DVVD is 1.8 V, the

DLDO1 and DLDO2 regulators must be disabled by setting

the PDN_LDO_DIG1 and PDN_LDO_DIG2 bits in the

POWERCONFIG register. DVDD, DLDO1, and DLDO2

are connected together.

POWER DOWN CAPABILITIES

The POWERCONFIG register lets the user place the AD9102 in a

reduced power dissipation configuration while the CLKP/CLKN

input is running and the power supplies are on. The DAC can be

put to sleep by setting the DAC_SLEEP bit in the POWERCONFIG

be turned on and off by setting the CLK_PDN bit in the

CLOCKCONFIG register. Taking these actions places the

AD9102 in the power down mode, specified in Table 8.

AD9102-EBZ Datasheet(PDF) 24 Page - Analog Devices

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