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HT66F20 Datasheet(PDF) 203 Page - Holtek Semiconductor Inc |
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HT66F20 Datasheet(HTML) 203 Page - Holtek Semiconductor Inc |
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203 / 298 page ![]() Rev. 1.90 �0� �e���a�� 18� �01� Rev. 1.90 �0� �e���a�� 18� �01� HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM HT66F20/HT66F30/HT66F40/HT66F50/HT66F60 HT66FU30/HT66FU40/HT66FU50/HT66FU60 Enhanced A/D Flash Type 8-Bit MCU with EEPROM Interrupts Interruptsareanimportantpartofanymicrocontrollersystem.Whenanexternaleventoran internalfunctionsuchasaTimerModuleoranA/Dconverterrequiresmicrocontrollerattention, theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogramallowingthe microcontrollertodirectattentiontotheirrespectiveneeds.Thedevicecontainsseveralexternal interruptandinternalinterruptsfunctions.Theexternalinterruptsaregeneratedbytheactionofthe externalINT0~INT3andPINTpins,whiletheinternalinterruptsaregeneratedbyvariousinternal functionssuchastheTMs,Comparators,TimeBase,LVD,EEPROM,SIMandtheA/Dconverter. Interrupt Registers Overallinterruptcontrol,whichbasicallymeansthesettingofrequestflagswhencertain microcontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram, iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshowninthe accompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfallintothree categories.ThefirstistheINTC0~INTC3registerswhichsetuptheprimaryinterrupts,thesecond istheMFI0~MFI3registerswhichsetuptheMulti-functioninterrupts.FinallythereisanINTEG registertosetuptheexternalinterrupttriggeredgetype. Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellas interruptflagstoindicatethepresenceofaninterruptrequest.Thenamingconventionofthese followsaspecificpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberof thatinterruptfollowedbyeitheran"E"forenable/disablebitor"F"forrequestflag. Function Enable Bit Request Flag Notes Glo�al EMI — — Compa�ato� CPnE CPn� n=0 o� 1 INTn Pin INTnE INTn� n=0~� A/D Conve�te� ADE AD� — M�lti-f�nction M�nE M�n� n=0~5 Time Base TBnE TBn� n=0 o� 1 SIM SIME SIM� — LVD LVE LV� — EEPROM DEE DE� — PINT Pin XPE XP� — TM TnPE TnP� n=0~� TnAE TnA� TnBE TnB� Interrupt Register Bit Naming Conventions |
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