AD5121 datasheet(10/32 Pages) AD

10 / 32 page

AD5121/AD5141

Data Sheet

Rev. 0 | Page 10 of 32

Parameter1

Test Conditions/Comments

Min

Typ

Max

Unit

Description

Standard mode

300

Fall time of SCL signal, t

FCL

Fast mode

20 + 0.1 C

300

Fast mode

Pulse width of suppressed spike (not shown in Figure 3)

1 Maximum bus capacitance is limited to 400 pF.

2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the

EMC behavior of the part.

3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.

Table 6. Control Pins

Parameter

Min

Typ

Max

Unit

Description

µs

End command to LRDAC falling edge

Minimum LRDAC low time

0.1

µs

RESET low time

tEEPROM_PROGRAM1

Memory program time (not shown in Figure 6)

tEEPROM_READBACK

µs

Memory readback time (not shown in Figure 6)

POWER_UP

µs

Power-on EEPROM restore time (not shown in Figure 6)

RESET

µs

Reset EEPROM restore time (not shown in Figure 6)

1 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.

2 Maximum time after V

DD − VSS is equal to 2.3 V.

SHIFT REGISTER AND TIMING DIAGRAMS

DATA BITS

DB8

DB15 (MSB)

DB0 (LSB)

ADDRESS BITS

CONTROL BITS

DB7

Figure 2. Input Shift Register Contents

t11

t12

t10

SCL

SDA

Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)

SDI

*PREVIOUS COMMAND RECEIVED.

SCLK

SYNC

C3*

SDO

C2*

C1*

C0*

D7*

D6*

D5*

D2*

D1*

D0*

t10

Figure 4. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1

AD5121 Datasheet(PDF) 10 Page - Analog Devices

AD5121 Datasheet(HTML) 10 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL