AT90CAN64 datasheet(22/431 Pages) ATMEL

22 / 431 page

7682C–AUTO–04/08

AT90CAN32/64/128

4.3

EEPROM Data Memory

The AT90CAN32/64/128 contains EEPROM memory (see “E2 size”). It is organized as a sepa-

rate data space, in which single bytes can be read and written. The EEPROM has an endurance

of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is

described in the following, specifying the EEPROM Address Registers, the EEPROM Data Reg-

ister, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

“SPI Serial Programming Overview” on page 347, “JTAG Programming Overview” on page 351,

and “Parallel Programming Overview” on page 338 respectively.

4.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 4-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instruc-

tions that write the EEPROM, some precautions must be taken. In heavily filtered power

supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specified as minimum for the clock frequency used.

See “Preventing EEPROM Corruption” on page 26.for details on how to avoid problems in these

situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

4.3.2

The EEPROM Address Registers – EEARH and EEARL

• Bits 15..12 – Reserved Bits

These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.

• Bits 11..0 – EEAR11..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the

EEPROM space (see “E2 size”). The EEPROM data bytes are addressed linearly between 0

and “E2 end”. The initial value of EEAR is undefined. A proper value must be written before the

EEPROM may be accessed.

– AT90CAN32: EEAR11 & EEAR10 exist as register bit but they are not used for

addressing.

– AT90CAN64: EEAR11 exists as register bit but it is not used for addressing.

Bit

–

EEAR11

EEAR10

EEAR9

EEAR8

EEARH

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEARL

Read/Write

R/W

Initial Value

AT90CAN64 Datasheet(PDF) 22 Page - ATMEL Corporation

AT90CAN64 Datasheet(HTML) 22 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL