AT90CAN64 datasheet(23/431 Pages) ATMEL

23 / 431 page

7682C–AUTO–04/08

AT90CAN32/64/128

4.3.3

The EEPROM Data Register – EEDR

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

4.3.4

The EEPROM Control Register – EECR

• Bits 7..4 – Reserved Bits

These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-

rupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written.

When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at

the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has

been written to one by software, hardware clears the bit to zero after four clock cycles. See the

description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address

and data are correctly set up, the EEWE bit must be written to one to write the value into the

EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, oth-

erwise no EEPROM write takes place. The following procedure should be followed when writing

the EEPROM (the order of steps 3 and 4 is not essential):

Wait until EEWE becomes zero.

Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Mem-

ory Control and Status Register) becomes zero.

Write new EEPROM address to EEAR (optional).

Write new EEPROM data to EEDR (optional).

Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Bit

EEDR7

EEDR6

EEDR5

EEDR4

EEDR3

EEDR2

EEDR1

EEDR0

EEDR

Read/Write

R/W

Initial Value

Bit

–

EERIE

EEMWE

EEWE

EERE

EECR

Read/Write

R/W

Initial Value

AT90CAN64 Datasheet(PDF) 23 Page - ATMEL Corporation

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