AT90CAN64 datasheet(30/431 Pages) ATMEL

30 / 431 page

7682C–AUTO–04/08

AT90CAN32/64/128

address actually is driven on the bus. The access time cannot exceed the time from the ALE

pulse must be asserted low until data is stable during a read sequence (see tLLRL+ tRLRH - tDVRH

in Tables 26-7 through Tables 26-14). The different wait-states are set up in software. As an

additional feature, it is possible to divide the external memory space in two sectors with individ-

ual wait-state settings. This makes it possible to connect two different memory devices with

different timing requirements to the same XMEM interface. For XMEM interface timing details,

please refer to Tables 26-7 through Tables 26-14 and Figure 26-6 to Figure 26-9 in the “External

Data Memory Characteristics” on page 374.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures

are related to the internal system clock. The skew between the internal and external clock

(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-

quently, the XMEM interface is not suited for synchronous operation.

Figure 4-6.

External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)(1)

Note:

1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction

accesses the RAM (internal or external).

Figure 4-7.

External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1(1)

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

XXXXX

XXXXXXXX

ALE

A15:8

Address

Prev. addr.

DA7:0

Address

Data

Prev. data

DA7:0 (XMBK = 0)

Data

Prev. data

Address

Data

Prev. data

Address

DA7:0 (XMBK = 1)

System Clock (CLKCPU)

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