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EP3SE110 Datasheet(PDF) 265 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 265 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–255
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–119 and Table 1–120 list the EP3SE80 regional clock (RCLK) adder values that
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–119 lists the EP3SE80 column pin delay adders when using the regional clock.
Table 1–120 lists the EP3SE80 row pin delay adders when using the regional clock.
EP3SE110 I/O Timing Parameters
Table 1–121 through Table 1–124 list the maximum I/O timing parameters for
EP3SE110 for single-ended I/O standards.
Table 1–121 lists the EP3SE110 column pins input timing parameters for single-ended
I/O standards.
Table 1–119. EP3SE80 Column Pin Delay Adders for Regional Clock
Parameter
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
RCLK input adder
0.251
0.187
0.308
0.239
0.389
0.103
0.176
0.199
0.102
0.099
0.172
ns
RCLK PLL input adder
1.895
1.982
2.923
3.16
3.601
4.28
4.913
3.261
4.491
4.295
4.833
ns
RCLK output adder
-0.069
0.253
0.551
0.865
0.693
-0.059
-0.119
1.06
0.135
0.066
-0.046
ns
RCLK PLL output adder
-1.545
-1.367
-1.715 -1.587 -1.976 -3.145
-3.116 -1.541 -3.343 -3.027 -3.123
ns
Table 1–120. EP3SE80 Row Pin Delay Adders for Regional Clock
Parameter
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
RCLK input adder
0.014
0.014
0.018
0.005
-0.022
0.0
0.052
-0.004 -0.014 -0.008
0.056
ns
RCLK PLL input adder
0.116
0.122
0.192
0.206
0.231
0.217
0.367
0.198
0.223
0.21
0.371
ns
RCLK output adder
0.004
0.003
0.029
0.042
0.056
0.039
-0.021
0.047
0.061
0.049
-0.025
ns
RCLK PLL output adder
-0.089
-0.089
-0.145 -0.161 -0.197 -0.169 -0.332 -0.151 -0.186 -0.157 -0.333
ns
Table 1–121. EP3SE110 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V LVTTL
GCLK
t
su
-1.030
-1.006
-1.454
-1.613
-1.847
-1.786
-2.148
-1.613 -1.847 -1.786 -2.148
ns
t
h
1.172
1.144
1.648
1.838
2.093
2.017
2.385
1.838
2.093
2.017
2.385
ns
GCLK
PLL
t
su
-1.297
-1.267
-1.831
-2.023
-2.261
-2.187
-2.655
-2.023 -2.261 -2.187 -2.655
ns
t
h
1.600
1.565
2.262
2.514
2.793
2.689
3.180
2.514
2.793
2.689
3.180
ns
3.3-V
LVCMOS
GCLK
t
su
-1.030
-1.006
-1.454
-1.613
-1.847
-1.786
-2.148
-1.613 -1.847 -1.786 -2.148
ns
t
h
1.172
1.144
1.648
1.838
2.093
2.017
2.385
1.838
2.093
2.017
2.385
ns
GCLK
PLL
t
su
-1.297
-1.267
-1.831
-2.023
-2.261
-2.187
-2.655
-2.023 -2.261 -2.187 -2.655
ns
t
h
1.600
1.565
2.262
2.514
2.793
2.689
3.180
2.514
2.793
2.689
3.180
ns



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