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EP3SE110 Datasheet(PDF) 266 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 266 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
3.0-V LVTTL
GCLK
t
su
-1.041
-1.017
-1.453
-1.615
-1.846
-1.785
-2.147
-1.615 -1.846 -1.785 -2.147
ns
t
h
1.183
1.155
1.647
1.840
2.092
2.016
2.384
1.840
2.092
2.016
2.384
ns
GCLK
PLL
t
su
-1.308
-1.278
-1.830
-2.025
-2.260
-2.186
-2.654
-2.025 -2.260 -2.186 -2.654
ns
t
h
1.611
1.576
2.261
2.516
2.792
2.688
3.179
2.516
2.792
2.688
3.179
ns
3.0-V
LVCMOS
GCLK
t
su
-1.041
-1.017
-1.453
-1.615
-1.846
-1.785
-2.147
-1.615 -1.846 -1.785 -2.147
ns
t
h
1.183
1.155
1.647
1.840
2.092
2.016
2.384
1.840
2.092
2.016
2.384
ns
GCLK
PLL
t
su
-1.308
-1.278
-1.830
-2.025
-2.260
-2.186
-2.654
-2.025 -2.260 -2.186 -2.654
ns
t
h
1.611
1.576
2.261
2.516
2.792
2.688
3.179
2.516
2.792
2.688
3.179
ns
2.5 V
GCLK
t
su
-1.036
-1.012
-1.462
-1.627
-1.865
-1.804
-2.166
-1.627 -1.865 -1.804 -2.166
ns
t
h
1.178
1.150
1.656
1.852
2.111
2.035
2.403
1.852
2.111
2.035
2.403
ns
GCLK
PLL
t
su
-1.303
-1.273
-1.839
-2.037
-2.279
-2.205
-2.673
-2.037 -2.279 -2.205 -2.673
ns
t
h
1.606
1.571
2.270
2.528
2.811
2.707
3.198
2.528
2.811
2.707
3.198
ns
1.8 V
GCLK
t
su
-1.058
-1.034
-1.502
-1.663
-1.863
-1.802
-2.164
-1.663 -1.863 -1.802 -2.164
ns
t
h
1.202
1.174
1.696
1.888
2.109
2.033
2.401
1.888
2.109
2.033
2.401
ns
GCLK
PLL
t
su
-1.325
-1.295
-1.879
-2.073
-2.277
-2.203
-2.671
-2.073 -2.277 -2.203 -2.671
ns
t
h
1.630
1.595
2.310
2.564
2.809
2.705
3.196
2.564
2.809
2.705
3.196
ns
1.5 V
GCLK
t
su
-1.048
-1.024
-1.479
-1.631
-1.793
-1.732
-2.094
-1.631 -1.793 -1.732 -2.094
ns
t
h
1.192
1.164
1.673
1.856
2.039
1.963
2.331
1.856
2.039
1.963
2.331
ns
GCLK
PLL
t
su
-1.315
-1.285
-1.856
-2.041
-2.207
-2.133
-2.601
-2.041 -2.207 -2.133 -2.601
ns
t
h
1.620
1.585
2.287
2.532
2.739
2.635
3.126
2.532
2.739
2.635
3.126
ns
1.2 V
GCLK
t
su
-0.996
-0.972
-1.402
-1.532
-1.637
-1.576
-1.938
-1.532 -1.637 -1.576 -1.938
ns
t
h
1.140
1.112
1.596
1.757
1.883
1.807
2.175
1.757
1.883
1.807
2.175
ns
GCLK
PLL
t
su
-1.263
-1.233
-1.779
-1.942
-2.051
-1.977
-2.445
-1.942 -2.051 -1.977 -2.445
ns
t
h
1.568
1.533
2.210
2.433
2.583
2.479
2.970
2.433
2.583
2.479
2.970
ns
SSTL-2
CLASS I
GCLK
t
su
-0.967
-0.943
-1.374
-1.516
-1.639
-1.578
-1.940
-1.516 -1.639 -1.578 -1.940
ns
t
h
1.111
1.083
1.568
1.741
1.885
1.809
2.177
1.741
1.885
1.809
2.177
ns
GCLK
PLL
t
su
-1.234
-1.204
-1.751
-1.926
-2.053
-1.979
-2.447
-1.926 -2.053 -1.979 -2.447
ns
t
h
1.539
1.504
2.182
2.417
2.585
2.481
2.972
2.417
2.585
2.481
2.972
ns
SSTL-2
CLASS II
GCLK
t
su
-0.967
-0.943
-1.374
-1.516
-1.639
-1.578
-1.940
-1.516 -1.639 -1.578 -1.940
ns
t
h
1.111
1.083
1.568
1.741
1.885
1.809
2.177
1.741
1.885
1.809
2.177
ns
GCLK
PLL
t
su
-1.234
-1.204
-1.751
-1.926
-2.053
-1.979
-2.447
-1.926 -2.053 -1.979 -2.447
ns
t
h
1.539
1.504
2.182
2.417
2.585
2.481
2.972
2.417
2.585
2.481
2.972
ns
SSTL-18
CLASS I
GCLK
t
su
-0.961
-0.937
-1.361
-1.508
-1.636
-1.573
-1.938
-1.508 -1.636 -1.573 -1.938
ns
t
h
1.105
1.077
1.555
1.730
1.879
1.803
2.170
1.730
1.879
1.803
2.170
ns
GCLK
PLL
t
su
-1.228
-1.198
-1.738
-1.918
-2.050
-1.974
-2.445
-1.918 -2.050 -1.974 -2.445
ns
t
h
1.533
1.498
2.169
2.406
2.579
2.475
2.965
2.406
2.579
2.475
2.965
ns
Table 1–121. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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