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EP3SE110 Datasheet(PDF) 268 Page - Altera Corporation

Part # EP3SE110
Description  Stratix III Device Handbook
PDF  341 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP3SE110 Datasheet(HTML) 268 Page - Altera Corporation

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1–258
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Table 1–122 lists the EP3SE110 row pins input timing parameters for single-ended I/O
standards.
3.0-V
PCI-X
GCLK
t
su
-1.041
-1.017
-1.453
-1.615
-1.846
-1.785
-2.147
-1.615 -1.846 -1.785 -2.147
ns
t
h
1.183
1.155
1.647
1.840
2.092
2.016
2.384
1.840
2.092
2.016
2.384
ns
GCLK
PLL
t
su
-1.308
-1.278
-1.830
-2.025
-2.260
-2.186
-2.654
-2.025 -2.260 -2.186 -2.654
ns
t
h
1.611
1.576
2.261
2.516
2.792
2.688
3.179
2.516
2.792
2.688
3.179
ns
Table 1–121. EP3SE110 Column Pins Input Timing Parameters (Part 4 of 4)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
Table 1–122. EP3SE110 Row Pins Input Timing Parameters (Part 1 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
3.3-V
LVTTL
GCLK
t
su
-0.917
-0.960
-1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064
ns
t
h
1.041
1.099
1.561
1.698
1.978
1.873
2.261
1.720
1.989
1.922
2.300
ns
GCLK
PLL
t
su
1.022
1.000
1.632
1.851
1.964
1.893
1.808
1.901
1.982
1.864
1.859
ns
t
h
-0.762
-0.722
-1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357
ns
3.3-V
LVCMOS
GCLK
t
su
-0.917
-0.960
-1.364 -1.476 -1.736 -1.642 -2.026 -1.488 -1.737 -1.683 -2.064
ns
t
h
1.041
1.099
1.561
1.698
1.978
1.873
2.261
1.720
1.989
1.922
2.300
ns
GCLK
PLL
t
su
1.022
1.000
1.632
1.851
1.964
1.893
1.808
1.901
1.982
1.864
1.859
ns
t
h
-0.762
-0.722
-1.218 -1.386 -1.449 -1.406 -1.309 -1.426 -1.456 -1.368 -1.357
ns
3.0-V
LVTTL
GCLK
t
su
-0.923
-0.971
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
ns
t
h
1.047
1.110
1.558
1.699
1.981
1.876
2.264
1.719
1.994
1.927
2.305
ns
GCLK
PLL
t
su
1.016
0.989
1.635
1.850
1.961
1.890
1.805
1.902
1.977
1.859
1.854
ns
t
h
-0.756
-0.711
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
ns
3.0-V
LVCMOS
GCLK
t
su
-0.923
-0.971
-1.361 -1.477 -1.739 -1.645 -2.029 -1.487 -1.742 -1.688 -2.069
ns
t
h
1.047
1.110
1.558
1.699
1.981
1.876
2.264
1.719
1.994
1.927
2.305
ns
GCLK
PLL
t
su
1.016
0.989
1.635
1.850
1.961
1.890
1.805
1.902
1.977
1.859
1.854
ns
t
h
-0.756
-0.711
-1.221 -1.385 -1.446 -1.403 -1.306 -1.427 -1.451 -1.363 -1.352
ns
2.5 V
GCLK
t
su
-0.911
-0.964
-1.370 -1.490 -1.754 -1.660 -2.044 -1.496 -1.752 -1.698 -2.079
ns
t
h
1.035
1.103
1.567
1.712
1.996
1.891
2.279
1.728
2.004
1.937
2.315
ns
GCLK
PLL
t
su
1.028
0.996
1.626
1.837
1.946
1.875
1.790
1.893
1.967
1.849
1.844
ns
t
h
-0.768
-0.718
-1.212 -1.372 -1.431 -1.388 -1.291 -1.418 -1.441 -1.353 -1.342
ns
1.8 V
GCLK
t
su
-0.987
-1.042
-1.456 -1.570 -1.756 -1.705 -2.042 -1.576 -1.754 -1.707 -2.080
ns
t
h
1.112
1.182
1.653
1.793
1.999
1.936
2.277
1.808
2.007
1.948
2.316
ns
GCLK
PLL
t
su
1.040
1.054
1.703
1.929
1.948
1.963
1.900
1.946
1.966
1.848
1.952
ns
t
h
-0.777
-0.773
-1.286 -1.461 -1.433 -1.472 -1.399 -1.468 -1.440 -1.352 -1.447
ns



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