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ATA5783 Datasheet(PDF) 13 Page - ATMEL Corporation

Part # ATA5783
Description  AVR microcontroller core with 1Kbyte SRAM and 24Kbyte RF library in firmware (ROM)
PDF  20 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

ATA5783 Datasheet(HTML) 13 Page - ATMEL Corporation

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Atmel ATA5781 [Summary DATASHEET]
9286BS–RKE–06/13
With the single pole double throw (SPDT) switch the RF signal from the antenna is switched to RFIN in RXMode.
The system is controlled by an AVR CPU with 24KB firmware ROM and 20KB user Flash for the Atmel® ATA5781, or with 20KB
user ROM for the Atmel ATA5782. 1024-byte EEPROM, 1024-byte SRAM, and other peripherals are supporting the receiver
handling. Two GPIO ports, PB[7:0] and PC[5:0], are available for external digital connections, for example, as an alternate
function the SPI interface is connected to port B. The Atmel ATA5781/2/3 is controlled by the EEPROM configuration and SPI
commands and the functional behavior is mainly determined by firmware in the ROM. Much of the configuration can be modified
by the EEPROM settings. The firmware running on the AVR gives access to the hardware functionality of the Atmel
ATA5781/2/3. Extensions to this firmware can be added in the 20KB of Flash memory for the Atmel ATA5781. The Rx DSP
registers are addressed directly and accessible from the AVR. A set of sequencer state machines is included to perform Rx path
operations (such as enable, disable, receive) which require a defined timing parallel to the AVR program execution.
The power management contains low-dropout (LDO) regulators and reset circuits for the supply voltages VS, AVCC, and DVCC
of the Atmel ATA5781/2/3. In OFFMode all the supply voltages AVCC and DVCC are switched off to achieve very low current
consumption. The Atmel ATA5781/2/3 can be powered up by activating the PWRON pin or one of the NPWRON[6:1] pins
because they are still active in OFFMode. The AVCC domain can be switched on and off independently from DVCC. The Atmel
ATA5781/2/3 includes two idle modes. In IDLEMode(RC) only the DVCC voltage regulator, the FRC and SRC oscillators are
active and the AVR uses a power-down mode to achieve low current consumption. The same power-down mode can be used
during the inactive phases of the PollingMode. In IDLEMode(XTO) the AVCC voltage domain as well as the XTO are
additionally activated.
An integrated watchdog timer is available to restart the Atmel ATA5781/2/3 when it is not served within the configured time-out
period.
3.2
Receive Path
3.2.1
Overview
The receive path consists of a low-noise amplifier (LNA), mixer, IF amplifier, analog-to-digital converter (ADC), and an Rx digital
signal processor (Rx DSP). The fractional-N PLL and the XTO deliver the local oscillator frequency in RXMode. The receive
path is controlled by the RF front-end registers.
Two separate LNA inputs, one for Low-Band and one for High-Band, are provided to obtain optimum performance matching for
each frequency range and to allow multi-band applications. A radio frequency (RF) level detector at the LNA output and a
switchable damping included into the single-pole double-trough (SPDT) switch is used in the presence of large blockers to
achieve enhanced system blocking performance.
The mixer converts the received RF signal to a low intermediate frequency (IF) of about 250kHz. A double-quadrature
architecture is used for the mixer to achieve high image rejection. Additionally, the third-order suppression of the local oscillator
(LO) harmonics makes receiving without a front-end SAW filter less critical, such as in a car key fob application.
An IF amplifier provides additional gain and improves the receiver sensitivity by 2-3dB. Because of built-in filter function, the in-
band compression is degraded by 10dB, while the out-of-band compression remains unchanged.
The ADC converts the IF signal into the digital domain. Due to the high effective resolution of the ADC, the channel filter and
received signal strength indicator (RSSI) can be realized in the digital signal domain. Therefore, no analog gain control (AGC)
potentially leading to critical timing issues or analog filtering is required in front of the ADC. This leads to a receiver front end
with excellent blocking performance up to the 1dB compression point of the LNA and mixer, and a steep digital channel filter can
be used.
The Rx DSP performs the channel filtering and converts the digital output signal of the ADC to the baseband for demodulation.
Due to the digital realization of these functions the Rx DSP can be adapted to the needs of many different applications. Channel
bandwidth, data rate, modulation type, wake-up criteria, signal checks, clock recovery, and many other properties are
configurable. The RSSI value is realized completely in the digital signal domain, enabling very high relative and absolute
accuracy that is only deteriorated by the gain errors of the LNA, mixer, and ADC.
Two independent receive paths A and B are integrated in the Rx DSP after the channel filter and allow the use of different data
rates, modulation types, and protocols without the need to power up the receive path more than once to decide which signal
should be received. This results in a reduced polling current in several applications.
The integration of remote keyless entry (RKE), passive entry and go (PEG) and tire-pressure monitoring systems (TPM) into
one module is simplified because completely different protocols can be supported and a low polling current is achieved. It is
even possible to configure different receive RF bands for different applications by using the two LNA inputs. For example, a
TPM receiver can be realized at 433.92MHz while a PEG system uses the 868MHz ISM band with multi-channel
communication.



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