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Atmel ATA5781 [Summary DATASHEET]

9286BS–RKE–06/13

3.2.2

Rx Digital Signal Processing (Rx DSP)

The Rx digital signal processing (DSP) block performs the digital filtering, decoding, checking, and byte-wise buffering of the Rx

samples that are derived from the ADC as shown in Figure 3-2. The Rx DSP provides the following outputs:

●

Raw demodulated data at the TRPA/B pins

●

Decoded data at the TMDO and TMDO_CLK pins

●

Buffered data bytes toward the data FIFO and ID check block

●

Auxiliary information about the signal such as the received signal strength indication (RSSI) and the frequency offset of

the received signal from the selected center frequency (RXFOA/B)

Figure 3-2.

Rx DSP Overview

The channel filter determines the receiver bandwidth. Its output is used for both receiving paths A and B, making it necessary to

configure the filter to match both paths. The receiving paths A and B are identical and consist of an ASK/FSK demodulator with

attached signal checks, a frame synchronizer which supports pattern-based searches for the telegram start and a 1-byte

hardware buffer with integrated CRC checker for the received data.

Depending on the signal checks, one path is selected which writes the received data to the data FIFO and optionally to the ID

check block.

The RSSI values are determined by the demodulator and written via the RSSI buffer to the support FIFO where the latest

16 values are stored for further processing.

TMDO_A

TMDO_CLK_A

TMDO_B

TMDO_CLK_B

RXFOA

TRPA

RXFOB

TRPB

RSSI

Demod

&

Check

Path

A

Data

Byte

Path

B

Rx

Buffer A

Rx

Buffer B

RSSI

Buffer

Frame

Sync A

Frame

Sync B

=

=

ID

Check

=

Support

FIFO

Data

FIFO

Data

Byte

Channel

Filter

ADC

Data