CC430F613 datasheet(62/120 Pages) TI

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SDA

SCL

HD,DAT

SU,DAT

HD,STA

HIGH

LOW

BUF

HD,STA

SU,STA

SU,STO

ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F613x

CC430F612x

CC430F513x

SLAS554G – MAY 2009 – REVISED FEBRUARY 2013

www.ti.com

USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 19)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Internal: SMCLK, ACLK

fUSCI

USCI input clock frequency

External: UCLK

fSYSTEM

MHz

Duty cycle = 50% ± 10%

fSCL

SCL clock frequency

2.2 V, 3 V

400

kHz

fSCL ≤ 100 kHz

4.0

tHD,STA

Hold time (repeated) START

2.2 V, 3 V

µs

fSCL > 100 kHz

0.6

fSCL ≤ 100 kHz

4.7

tSU,STA

Setup time for a repeated START

2.2 V, 3 V

µs

fSCL > 100 kHz

0.6

tHD,DAT

Data hold time

2.2 V, 3 V

tSU,DAT

Data setup time

2.2 V, 3 V

250

fSCL ≤ 100 kHz

4.0

tSU,STO

Setup time for STOP

2.2 V, 3 V

µs

fSCL > 100 kHz

0.6

2.2 V

600

tSP

Pulse width of spikes suppressed by input filter

3 V

600

Figure 19. I2C Mode Timing

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