CC430F613 datasheet(22/120 Pages) TI

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ECCN 5E002 TSPA - Technology / Software Publicly Available

CC430F613x

CC430F612x

CC430F513x

SLAS554G – MAY 2009 – REVISED FEBRUARY 2013

www.ti.com

Table 10. Port Mapping, Mnemonics and Functions (continued)

OUTPUT PIN FUNCTION

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION (PxDIR.y=0)

(PxDIR.y=1)

Reserved

None

DVSS

Reserved

None

DVSS

Reserved

None

DVSS

Reserved

None

DVSS

Disables the output driver as well as the input Schmitt-trigger to prevent

31 (0FFh)(6)

PM_ANALOG

parasitic cross currents when applying analog signals.

(6)

The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored

resulting in a read out value of 31.

Table 11. Default Mapping

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PxMAPy MNEMONIC

(PxDIR.y=0)

(PxDIR.y=1)

P1.0/P1MAP0

PM_RFGDO0

None

Radio GDO0

P1.1/P1MAP1

PM_RFGDO2

None

Radio GDO2

USCI_B0 SPI slave out master in (direction controlled by USCI),

P1.2/P1MAP2

PM_UCB0SOMI/PM_UCB0SCL

USCI_B0 I2C clock (open drain and direction controlled by USCI)

USCI_B0 SPI slave in master out (direction controlled by USCI),

P1.3/P1MAP3

PM_UCB0SIMO/PM_UCB0SDA

USCI_B0 I2C data (open drain and direction controlled by USCI)

USCI_B0 clock input/output (direction controlled by USCI),

P1.4/P1MAP4

PM_UCB0CLK/PM_UCA0STE

USCI_A0 SPI slave transmit enable (direction controlled by USCI - input)

USCI_A0 UART RXD (Direction controlled by USCI - input),

P1.5/P1MAP5

PM_UCA0RXD/PM_UCA0SOMI

USCI_A0 SPI slave out master in (direction controlled by USCI)

USCI_A0 UART TXD (Direction controlled by USCI - output),

P1.6/P1MAP6

PM_UCA0TXD/PM_UCA0SIMO

USCI_A0 SPI slave in master out (direction controlled by USCI)

USCI_A0 clock input/output (direction controlled by USCI),

P1.7/P1MAP7

PM_UCA0CLK/PM_UCB0STE

USCI_B0 SPI slave transmit enable (direction controlled by USCI - input)

P2.0/P2MAP0

PM_CBOUT1/PM_TA1CLK

TA1 clock input

Comparator_B output

P2.1/P2MAP1

PM_TA1CCR0A

TA1 CCR0 capture input CCI0A

TA1 CCR0 compare output Out0

P2.2/P2MAP2

PM_TA1CCR1A

TA1 CCR1 capture input CCI1A

TA1 CCR1 compare output Out1

P2.3/P2MAP3

PM_TA1CCR2A

TA1 CCR2 capture input CCI2A

TA1 CCR2 compare output Out2

P2.4/P2MAP4

PM_RTCCLK

None

RTCCLK output

P2.5/P2MAP5

PM_SVMOUT

None

SVM output

P2.6/P2MAP6

PM_ACLK

None

ACLK output

P2.7/P2MAP7

PM_ADC12CLK/PM_DMAE0

DMA external trigger input

ADC12CLK output

P3.0/P3MAP0

PM_CBOUT0/PM_TA0CLK

TA0 clock input

Comparator_B output

P3.1/P3MAP1

PM_TA0CCR0A

TA0 CCR0 capture input CCI0A

TA0 CCR0 compare output Out0

P3.2/P3MAP2

PM_TA0CCR1A

TA0 CCR1 capture input CCI1A

TA0 CCR1 compare output Out1

P3.3/P3MAP3

PM_TA0CCR2A

TA0 CCR2 capture input CCI2A

TA0 CCR2 compare output Out2

P3.4/P3MAP4

PM_TA0CCR3A

TA0 CCR3 capture input CCI3A

TA0 CCR3 compare output Out3

P3.5/P3MAP5

PM_TA0CCR4A

TA0 CCR4 capture input CCI4A

TA0 CCR4 compare output Out4

P3.6/P3MAP6

PM_RFGDO1

None

Radio GDO1

P3.7/P3MAP7

PM_SMCLK

None

SMCLK output

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