MAX1021 datasheet(18/40 Pages) MAXIM

18 / 40 page

10-Bit, Multichannel ADCs/DACs with FIFO,

Temperature Sensing, and GPIO Ports

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Table 1. Command Byte (MSB First)

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Conversion

CHSEL2

CHSEL1

CHSEL0

SCAN1

SCAN0

TEMP

Setup

CKSEL1

CKSEL0

REFSEL1

REFSEL0

DIFFSEL1

DIFFSEL0

ADC Averaging

AVGON

NAVG1

NAVG0

NSCAN1

NSCAN0

DAC Select

XXXX

Reset

RESET

SLOW

FBGON

GPIO Configure

000011

GPIO Write

000010

GPIO Read

000001

No Operation

000000

X = Don’t care.

Power-Up Default State

The MAX1021/MAX1043 power up with all blocks in

shutdown (including the reference). All registers power

up in state 00000000, except for the setup register and

the DAC input register. The setup register powers up at

00101000 with CKSEL1 = 1 and REFSEL1 = 1. The

DAC input register powers up to 3FFh when RES_SEL

is high, and it powers up to 000h when RES_SEL is low.

10-Bit ADC

The MAX1021/MAX1043 ADCs use a fully differential

successive-approximation register (SAR) conversion

technique and on-chip track-and-hold (T/H) circuitry to

convert temperature and voltage signals into 10-bit dig-

ital results. The analog inputs accept both single-ended

and differential input signals. Single-ended signals are

converted using a unipolar transfer function, and differ-

ential signals are converted using a selectable bipolar

or unipolar transfer function. See the

ADC Transfer

Functions section for more data.

ADC Clock Modes

When addressing the setup, register bits 5 and 4 of the

command byte (CKSEL1 and CKSEL0, respectively)

control the ADC clock modes. See Table 5. Choose

between four different clock modes for various ways to

start a conversion and determine whether the acquisi-

tions are internally or externally timed. Select clock

mode 00 to configure

CNVST/AIN_ to act as a conver-

sion start and use it to request internally timed conver-

sions, without tying up the serial bus. In clock mode 01,

use

CNVST to request conversions one channel at a

time, thereby controlling the sampling speed without

tying up the serial bus. Request and start internally

timed conversions through the serial interface by writ-

ing to the conversion register in the default clock mode,

10. Use clock mode 11 with SCLK up to 3.6MHz for

externally timed acquisitions to achieve sampling rates

up to 225ksps. Clock mode 11 disables scanning and

averaging. See Figures 6–9 for timing specifications on

how to begin a conversion.

These devices feature an active-low, end-of-conversion

output.

EOC goes low when the ADC completes the last

requested operation and is waiting for the next com-

mand byte.

EOC goes high when CS or CNVST go low.

EOC is always high in clock mode 11.

Single-Ended or Differential Conversions

The MAX1021/MAX1043 use a fully differential ADC for

all conversions. When a pair of inputs are connected as

a differential pair, each input is connected to the ADC.

When configured in single-ended mode, the positive

input is the single-ended channel and the negative

input is referred to AGND. See Figure 2.

In differential mode, the T/H samples the difference

between two analog inputs, eliminating common-mode

DC offsets and noise. IN+ and IN- are selected from the

following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,

AIN6/AIN7. See Tables 5–8 for more details on config-

uring the inputs. For the inputs that are configurable as

CNVST, REF2, and an analog input, only one function

can be used at a time.

MAX1021 Datasheet(PDF) 18 Page - Maxim Integrated Products

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