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MAX1021 Datasheet(PDF) 33 Page - Maxim Integrated Products

Part # MAX1021
Description  10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
PDF  40 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1021 Datasheet(HTML) 33 Page - Maxim Integrated Products

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10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
______________________________________________________________________________________
33
Initiate a scan by writing a command byte to the conver-
sion register. The MAX1021/MAX1043 then power up,
scan all requested channels, store the results in the
FIFO, and shut down. After the scan is complete,
EOC is
pulled low and the results are available in the FIFO. If a
temperature measurement is requested, the tempera-
ture result precedes all other FIFO results. Temperature
results are available in 12-bit format.
EOC stays low until
CS is pulled low again. Wait until all conversions are
complete before reading the FIFO. SPI communications
to the DAC and GPIO registers are permitted during
conversion. However, coupled noise may result in
degraded ADC SNR.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are
initiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging, and the
FIFO are disabled, and the conversion result is avail-
able at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figure 9 for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If
CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
DOUT
MSB1
tRDS
LSB1
MSB2
SCLK
CNVST
EOC
Figure 6. Clock Mode 00—After writing a command byte, set
CNVST low for at least 40ns to begin a conversion.
(CONVERSION 2)
tCSW
tDOV
(ACQUISITION 2)
(ACQUISITION 1)
(CONVERSION 1)
CS
DOUT
MSB1
LSB1
MSB2
SCLK
CNVST
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting
CNVST low for each conversion.



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