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MAX1021 Datasheet(PDF) 6 Page - Maxim Integrated Products

Part # MAX1021
Description  10-Bit, Multichannel ADCs/DACs with FIFO, Temperature Sensing, and GPIO Ports
PDF  40 Pages
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Manufacturer  MAXIM [Maxim Integrated Products]
Direct Link  https://www.maximintegrated.com/en.html
Logo MAXIM - Maxim Integrated Products

MAX1021 Datasheet(HTML) 6 Page - Maxim Integrated Products

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10-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = 2.7V to 5.25V, external reference VREF = 2.5V, fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C, unless
otherwise noted. Typical values are at AVDD = DVDD = 3V, TA = +25°C. Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage
DVDD
2.7
AVDD
V
Idle, all blocks shut down
0.2
4
µA
Digital Positive-Supply Current
DIDD
Only ADC on, external reference
1
mA
Analog Positive-Supply Voltage
AVDD
2.70
5.25
V
Idle, all blocks shut down
0.2
2
µA
fSAMPLE = 225ksps
2.8
4.2
Only ADC on,
external reference
fSAMPLE = 100ksps
2.6
Analog Positive-Supply Current
AIDD
All DACs on, no load, internal reference
1.5
4.0
mA
REF1 Positive-Supply Rejection
PSRR
AVDD = 2.7V
-77
dB
DAC Positive-Supply Rejection
PSRD
Output
code =
FFFhex
AVDD = 2.7V to 5.25V
±0.1
±0.5
mV
ADC Positive-Supply Rejection
PSRA
Full-
scale
input
AVDD = 2.7V to 5.25V
±0.06
±0.5
mV
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
tCP
40
ns
SCLK Pulse-Width High
tCH
40/60 duty cycle
16
ns
SCLK Pulse-Width Low
tCL
60/40 duty cycle
16
ns
GPIO Output Rise/Fall After
CS Rise
tGOD
CLOAD = 20pF
100
ns
GPIO Input Setup Before
CS Fall
tGSU
0ns
LDAC Pulse Width
tLDACPWL
20
ns
CLOAD = 20pF, SLOW = 0
1.8
12.0
SCLK Fall to DOUT Transition
(Note 16)
tDOT
CLOAD = 20pF, SLOW = 1
10
40
ns
CLOAD = 20pF, SLOW = 0
1.8
12.0
SCLK Rise to DOUT Transition
(Notes 16, 17)
tDOT
CLOAD = 20pF, SLOW = 1
10
40
ns
CS Fall to SCLK Fall Setup Time
tCSS
10
ns
SCLK Fall to
CS Rise Setup
Time
tCSH
0
2000
ns
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
0ns
CS Pulse-Width High
tCSPWH
50
ns
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
25
ns
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
1.5
25.0
ns
EOC Fall to CS Fall
tRDS
30
ns



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