BF516F datasheet(13/68 Pages) AD

13 / 68 page

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

Rev. B

Page 13 of 68

January 2011

TNOM is the duration running at fCCLKNOM

TRED is the duration running at fCCLKRED

VOLTAGE REGULATION INTERFACE

The ADSP-BF51x processors require an external voltage regula-

tor to power the VDDINT domain. To reduce standby power

consumption in the hibernate state, the external voltage regula-

tor can be signaled through EXT_WAKE to remove power from

the processor core. The EXT_WAKE signal is high-true for

power-up and may be connected directly to the low-true shut

down input of many common regulators.

The Power Good (PG) input signal allows the processor to start

only after the internal voltage has reached a chosen level. In this

way, the startup time of the external regulator is detected after

hibernation. For a complete description of the PG functionality,

refer to the ADSP-BF51x Blackfin Processor Hardware Reference.

CLOCK SIGNALS

The ADSP-BF51x processors can be clocked by an external crys-

tal, a sine wave input, or a buffered, shaped clock derived from

an external clock oscillator.

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor CLKIN signal. When an external

clock is used, the XTAL pin/ball must be left unconnected.

Alternatively, because the processor includes an on-chip oscilla-

tor circuit, an external crystal may be used. For fundamental

frequency operation, use the circuit shown in Figure 4. A paral-

lel-resonant, fundamental frequency, microprocessor-grade

crystal is connected across the CLKIN and XTAL pins/balls. The

on-chip resistance between the CLKIN pin/ball and the XTAL

pin/ball is in the 500 kΩ range. Further parallel resistors are typ-

ically not recommended. The two capacitors and the series

resistor shown in Figure 4 fine tune phase and amplitude of the

sine frequency.

The capacitor and resistor values shown in Figure 4 are typical

values only. The capacitor values are dependent upon the crystal

manufacturers’ load capacitance recommendations and the PCB

physical layout. The resistor value depends on the drive level

specified by the crystal manufacturer. The user should verify the

customized values based on careful investigations on multiple

devices over temperature range.

A third-overtone crystal can be used for frequencies above 25

MHz. The circuit is then modified to ensure crystal operation

only at the third overtone, by adding a tuned inductor circuit as

shown in Figure 4. A design procedure for third-overtone oper-

ation is discussed in detail in application note (EE-168) Using

Third Overtone Crystals with the ADSP-218x DSP on the Analog

Devices website (www.analog.com)—use site search on

“EE-168.”

The CLKBUF signal is an output signal, which is a buffered ver-

sion of the input clock. This signal is particularly useful in

Ethernet applications to limit the number of required clock

sources in the system. In this type of application, a single

25 MHz or 50 MHz crystal may be applied directly to the pro-

cessor. The 25 MHz or 50 MHz output of CLKBUF can then be

connected to an external Ethernet MII or RMII PHY device.

The Blackfin core runs at a different clock rate than the on-chip

peripherals. As shown in Figure 5, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a programmable 5× to 64× multiplication

factor (bounded by specified minimum and maximum VCO

frequencies). The default multiplier is 6×, but it can be modified

by a software instruction sequence.

On-the-fly frequency changes can be done simply by writing to

the PLL_DIV register. The maximum allowed CCLK and SCLK

rates depend on the applied voltages VDDINT, VDDEXT, and

VDDMEM, and the VCO is always permitted to run up to the fre-

quency specified by the part’s speed grade. The CLKOUT signal

reflects the SCLK frequency to the off-chip world. It belongs to

the SDRAM interface, but it functions as a reference signal in

other timing specifications as well. While active by default, it

can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL

registers.

Figure 4. External Crystal Connections

Figure 5. Frequency Modification Methods

CLKIN

CLKOUT

XTAL

CLKBUF

TO PLL CIRCUITRY

FOR OVERTONE

OPERATION ONLY:

NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED, DEPENDING

ON THE CRYSTAL AND LAYOUT. PLEASE ANALYZE CAREFULLY. FOR

FREQUENCIES ABOVE 33 MHz, THE SUGGESTED CAPACITOR VALUE

OF 18 pF SHOULD BE TREATED AS A MAXIMUM, AND THE SUGGESTED

RESISTOR VALUE SHOULD BE REDUCED TO 0

18 pF *

330

BLACKFIN

560

PLL

u to 64u

÷1 to 15

÷1,2, 4, 8

VCO

CLKIN

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

CCLK

SCLK

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