| Electronic Components Datasheet Search |
|
BF516F Datasheet(PDF) 19 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
BF516F Datasheet(HTML) 19 Page - Analog Devices |
|
19 / 68 page ![]() ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F Rev. B | Page 19 of 68 | January 2011 Port J PJ0:SCL I/O 5V TWI Serial Clock (This signal is an open-drain output and requires a pull-up resistor. Consult version 2.1 of the I 2C specification for the proper resistor value.) E PJ1:SDA I/O 5V TWI Serial Data (This signal is an open-drain output and requires a pull-up resistor. Consult version 2.1 of the I 2C specification for the proper resistor value.) E Real Time Clock RTXI I RTC Crystal Input (This ball should be pulled low when not used.) RTXO O RTC Crystal Output (Does not three-state during hibernate) JTAG Port TCK I JTAG Clock TDO O JTAG Serial Data Out C TDI I JTAG Serial Data In TMS I JTAG Mode Select TRST I JTAG Reset (This signal should be pulled low if the JTAG port is not used.) EMU O Emulation Output C Clock CLKIN I Clock/Crystal Input XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate) CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate) C Mode Controls RESET I Reset NMI I Non-maskable Interrupt (This signal should be pulled high when not used.) BMODE2-0 I Boot Mode Strap 2-0 Voltage Regulation Interface PG I Power Good (This signal should be pulled low when not used.) EXT_WAKE O Wake up Indication (Does not three-state during hibernate) C Power Supplies ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page 20. VDDEXT PI/O Power Supply VDDINT P Internal Power Supply VDDRTC P Real Time Clock Power Supply VDDFLASH P Internal SPI Flash Power Supply VDDMEM PMEM Power Supply VPPOTP P OTP Programming Voltage VDDOTP POTP Power Supply GND G Ground for All Supplies 1 See Output Drive Currents on Page 50 for more information about each driver type. 2 When driven low, the PF15 signal can be used to wake up the processor from the hibernate state, either in normal GPIO mode or in Ethernet mode as PHYINT. If the pin/ball is used for wake up, enable the feature with the PHYWE bit in the VR_CTL register, and pull-up the signal with a resistor. 3 Boot host wait is a GPIO signal toggled by the boot kernel. The mandatory external pull-up/pull-down resistor defines the signal polarity. 4 A pull-up resistor is required for the boot from external SPI EEPROM or flash (BMODE = 0x3). Table 7. Signal Descriptions Signal Name Type Function Driver Type1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |