BF516F datasheet(33/68 Pages) AD

33 / 68 page

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

Rev. B

Page 33 of 68

January 2011

Parallel Peripheral Interface Timing

Table 30 and Figure 15 on Page 33, Figure 21 on Page 38, and

Figure 24 on Page 40 describe parallel peripheral interface

operations.

Table 30. Parallel Peripheral Interface Timing

VDDEXT

1.8 V Nominal

VDDEXT

2.5 V/3.3 V Nominal

Parameter

Min

Max

Min

Max

Unit

Timing Requirements

tPCLKW

PPI_CLK Width

tSCLK – 1.5

tPCLK

PPI_CLK Period

2 × tSCLK – 1.5

Timing Requirements - GP Input and Frame Capture Modes

tPSUD

External Frame Sync Startup Delay1

4 × tPCLK

tSFSPE

External Frame Sync Setup Before PPI_CLK

(Nonsampling Edge for Rx, Sampling Edge for Tx)

6.7

tHFSPE

External Frame Sync Hold After PPI_CLK

1.75

tSDRPE

Receive Data Setup Before PPI_CLK

4.1

3.5

tHDRPE

Receive Data Hold After PPI_CLK

1.6

Switching Characteristics - GP Output and Frame Capture Modes

tDFSPE

Internal Frame Sync Delay After PPI_CLK

tHOFSPE

Internal Frame Sync Hold After PPI_CLK

1.7

tDDTPE

Transmit Data Delay After PPI_CLK

8.2

tHDTPE

Transmit Data Hold After PPI_CLK

2.3

1.9

1 The PPI port is fully enabled 4 PPI clock cycles after the PAB write to the PPI port enable bit. Only after the PPI port is fully enabled are external frame syncs and data words

guaranteed to be received correctly by the PPI peripheral.

Figure 14. PPI with External Frame Sync Timing

Figure 15. PPI GP Rx Mode with External Frame Sync Timing

PPI_CLK

PPI_FS1/2

tPSUD

tPCLK

tSFSPE

DATA SAMPLED /

FRAME SYNC SAMPLED

DATA SAMPLED /

FRAME SYNC SAMPLED

PPI_DATA

PPI_CLK

PPI_FS1/2

tHFSPE

tHDRPE

tSDRPE

tPCLKW

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