LM3405A

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SNVS508C – OCTOBER 2007 – REVISED MAY 2013

If the inductor ripple current is fairly small (for example, less than 40%) , the conduction loss can be simplified to:

(22)

The switching loss occurs during the switch on and off transition periods, where voltage and current overlap

resulting in power loss. The simplest means to determine this loss is to empirically measure the rise and fall

times (10% to 90%) of the voltage at the switch pin.

Switching power loss is calculated as follows:

(23)

(24)

The power loss required for operation of the internal circuitry:

(25)

The total power loss in the IC is:

(26)

An example of power losses for a typical application is shown in Table 2:

Table 2. Power Loss Tabulation

Conditions

Power loss

12V

3.9V

1.0A

0.45V

300m

Ω

108mW

1.6MHz

18ns

288mW

12ns

1.8mA

22mW

1.4nC

27mW

D is calculated to be 0.36

(27)

(28)

PCB Layout Considerations

When planning the layout there are a few things to consider when trying to achieve a clean, regulated output.

The most important consideration when completing the layout is the close coupling of the GND connections of

the input capacitor C1 and the catch diode D1. These ground ends should be close to one another and be

connected to the GND plane with at least two through-holes. Place these components as close to the IC as

possible. The next consideration is the location of the GND connection of the output capacitor C2, which should

be near the GND connections of C1 and D1.

There should be a continuous ground plane on the bottom layer of a two-layer board except under the switching

node island.

The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise pickup

that causes inaccurate regulation. The LED current setting resistor R1 should be placed as close as possible to

should be routed away from the inductor and any other traces that are switching.

Radiated noise can be decreased by choosing a shielded inductor.

The remaining components should also be placed as close as possible to the IC. See Application Report AN-

1229 (SNVA054) for further considerations and the LM3405A demo board as an example of a four-layer layout.

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