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AT90USB646 Datasheet(PDF) 136 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 136 Page - ATMEL Corporation |
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136 / 456 page ![]() 136 7593L–AVR–09/12 AT90USB64/128 Figure 15-13. Timer/Counter timing diagram, with prescaler (f clk_I/O/8). 15.10 16-bit Timer/Counter register description 15.10.1 TCCR1A – Timer/Counter1 Control Register A 15.10.2 TCCR3A – Timer/Counter3 Control Register A • Bit 7:6 – COMnA1:0: Compare Output Mode for Channel A • Bit 5:4 – COMnB1:0: Compare Output Mode for Channel B • Bit 3:2 – COMnC1:0: Compare Output Mode for Channel C The COMnA1:0, COMnB1:0, and COMnC1:0 control the output compare pins (OCnA, OCnB, and OCnC respectively) behavior. If one or both of the COMnA1:0 bits are written to one, the OCnA output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COMnB1:0 bits are written to one, the OCnB output overrides the normal port func- tionality of the I/O pin it is connected to. If one or both of the COMnC1:0 bits are written to one, the OCnC output overrides the normal port functionality of the I/O pin it is connected to. How- ever, note that the Data Direction Register (DDR) bit corresponding to the OCnA, OCnB or OCnC pin must be set in order to enable the output driver. TOVn(FPWM) and ICF n(if used as TOP) OCRnx (update at TOP) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP TOP - 1 TOP - 2 Old OCRnx value New OCRnx value TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O /8) Bit 7 65 43 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 TCCR1A Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 000 0 Bit 7 65 43 2 1 0 COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 TCCR3A Read/write R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00 00 000 0 |
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