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AT90USB646 Datasheet(PDF) 211 Page - ATMEL Corporation |
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AT90USB646 Datasheet(HTML) 211 Page - ATMEL Corporation |
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211 / 456 page ![]() 211 7593L–AVR–09/12 AT90USB64/128 21. 2-wire serial interface 21.1 Features • Simple yet powerful and flexible communication interface, only two bus lines needed • Both Master and Slave operation supported • Device can operate as transmitter or receiver • 7-bit address space allows up to 128 different slave addresses • Multi-master arbitration support • Up to 400kHz data transfer speed • Slew-rate limited output drivers • Noise suppression circuitry rejects spikes on bus lines • Fully programmable slave address with general call support • Address recognition causes wake-up when AVR is in sleep mode 21.2 2-wire Serial Interface bus definition The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard- ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol. Figure 21-1. TWI bus interconnection. 21.2.1 TWI terminology The following definitions are frequently encountered in this section. The Power Reduction TWI bit, PRTWI bit in “PRR0 – Power Reduction Register 0” on page 54 must be written to zero to enable the 2-wire Serial Interface. Device 1 Device 2 Device 3 Device n SDA SCL ........ R1 R2 V CC Table 21-1. TWI terminology. Term Description Master The device that initiates and terminates a transmission. The Master also generates the SCL clock. Slave The device addressed by a Master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus. |
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