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AT90USB646 Datasheet(PDF) 214 Page - ATMEL Corporation

Part # AT90USB646
Description  8-bit Atmel Microcontroller with 64/128Kbytes of ISP Flash and USB Controller
PDF  456 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

AT90USB646 Datasheet(HTML) 214 Page - ATMEL Corporation

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214
7593L–AVR–09/12
AT90USB64/128
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 21-5. Data packet format.
21.3.5
Combining address and data packets into a transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condi-
tion, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 21-6 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol imple-
mented by the application software.
Figure 21-6. Typical data transmission.
12
78
9
Data MSB
Data LSB
ACK
Aggregate
SDA
SDA from
transmitter
SDA from
receiver
SCL from
master
SLA+R/W
Data byte
STOP, REPEATED
START or next
data byte
12
7
8
9
Data byte
Data MSB
Data LSB
ACK
SDA
SCL
START
12
789
Addr MSB
Addr LSB
R/W
ACK
SLA+R/W
STOP



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