AT90USB646 datasheet(213/456 Pages) ATMEL

213 / 456 page

213

7593L–AVR–09/12

AT90USB64/128

Figure 21-3. START, REPEATED START and STOP conditions.

21.3.3

Address packet format

All address packets transmitted on the TWI bus are nine bits long, consisting of seven address

bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read

operation is to be performed, otherwise a write operation should be performed. When a Slave

recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL

(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Mas-

ter’s request, the SDA line should be left high in the ACK clock cycle. The Master can then

transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An

address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or

SLA+W, respectively.

The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the

designer, but the address 0000 000 is reserved for a general call.

When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK

cycle. A general call is used when a Master wishes to transmit the same message to several

slaves in the system. When the general call address followed by a Write bit is transmitted on the

bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.

The following data packets will then be received by all the slaves that acknowledged the general

call. Note that transmitting the general call address followed by a Read bit is meaningless, as

this would cause contention if several slaves started transmitting different data.

All addresses of the format 1111 xxx should be reserved for future purposes.

Figure 21-4. Address packet format.

21.3.4

Data packet format

All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and

an acknowledge bit. During a data transfer, the Master generates the clock and the START and

SDA

SCL

START

STOP

REPEATED START

STOP

START

SDA

SCL

START

Addr MSB

Addr LSB

R/W

ACK

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