MD3872 datasheet(13/24 Pages) SUTEX

13 / 24 page

Supertex inc.

www.supertex.com

MD3872

Doc.# DSFP-MD3872

B060413

General Description

The MD3872 has eight identical front-end receiver channels

designed for medical ultrasound imaging. Each channel con-

sists of a low noise preamplifier (LNA), a variable gain ampli-

fier (VGA), an anti-aliasing filter (AAF), and a 12-bit analog-

to-digital converter (ADC). The VGA consists of two parts, a

voltage controlled attenuator (VCA), and a programmable

gain amplifier (PGA). The gain and gain range of the VGA

can be digitally configured separately. The gain of the LNA

is selectable. The differential outputs of each LNA can also

be used to provide amplified RF signals for the CW Doppler

beamforming processing. The voltage-controlled-gain TGC

attenuator can be continuously varied by a control voltage at

the TGC pin from -47dB to a maximum of 0dB. The gain of

the TGC curve is linear-in-dB, and the slope of the curve can

be adjusted by the input voltage of GSC pin for all the eight

channels in the same chip.

The TGC attenuator output is AC-coupled into the PGA.

PGA gain is programmed through the two gain bits (PG0

and PG1) in the SPI control register, and can be configured

to four different gain settings of 23.5, 29, 34.5 and 40dB.

The AAF is a third-order Butterworth low-pass filter. The au-

to-tracking cutoff frequency is typically one-third of the sam-

pling frequency, and is typically triggered by the FLEX com-

mand calibration. There are control bits in SPI for adjusting

the auto-tracking cutoff frequency up to ±15% of the typical

value for the anti-aliasing filter. In addition, the SPI control

The ADC converters in the MD3872 use a very low power,

high-speed, self-calibrated pipeline architecture that moves

the samples through the pipeline stages every half clock-

cycle. The converted digital results are serialized and sent

through the LVDS output drivers. The total latency is 5.5 in-

put clock cycles.

The following sections are detail descriptions of each pro-

grammable feature.

LNA Gain & Active Impedance Matching

The LNA consists of a differential voltage gain low noise am-

plifier. The LNA’s inverting single-ended output gain is A =

4.0 and A = 2.5 when the LNA differential gain is 18dB and

14dB, respectively. With a known fixed gain, a feedback re-

sistor can be connected between the LNA positive input pin

(IN1+) and the inverting output pin (PA1-), and in series with

a capacitor. This technique is well known as active termina-

tion and results in a better noise figure (NF) than passive

termination. The effective input resistance is RIN = RFB/

(1+A). In addition, the MD3872 provides a dual mode feed-

back resistor option for connecting two feedback resistors in

parallel through the SWx pins. The SWx pin is connected to

the PAx pin with an internal switch which is controlled by the

SWLNA bit in SPI.

TGC / CW Mode & Power Consumption

At power up, all the SPI register’s data bits are reset to 0, and

the MD3872 will go into the default: all TGC mode and the

whole chip’s current consumption is approximately 760mW

if the sampling clock is 40MHz. When in the default state,

CW/TGC = 0, (ADDR=6, D[7:0]=’00000000’), ADCPD[7:0]

=’00000000’, all channels of LNA, VGA, AAF and ADC are

turned on. At the same time, PLL and LVDS will be turned

on in this mode.

To control each TGC (LNA+VGA+AAF) channel individually,

ADDR = 6, CHOFF[7:0] provides selection of turning ON/

OFF for each TGC channel. For example, when MD3872 is

in TGC mode, CW/TGC = 0 and CHOFF[7:0] = ’01111111’,

only the TGC channel 8 is switched ON and other channels

are switched OFF. In this condition, the whole chip’s current

consumption will be quite a bit less than when all channels

are ON. To power off each ADC individually in TGC mode,

ADDR = 9, ADCPD[7:0] can be programmed to state1. For

example, ADCPD[7:0] = ’10000000’, ADC8 is powered down

and the others are powered on. Note that in TGC mode,

ADDR = 2, 3, 4 and 5 are meaningless.

If CW/TGC = 1, MD3872 will go into CW mode, all the VGA,

ADC, AFF, LVDS and PLL will be shut down automatically

and ADDR = 6, D[7:0] is meaningless. In CW mode, each

channel’s CW trans-conductance amplifiers ON and OFF

are controlled by ADDR = 2,3,4 and 5 as shown in the CW

cross-point switch control register table. For example, if CW/

TGC = 1, ADDR 2, D[11:0] =’100000100000’, the MD3872

will be in CW mode and CW channels 1 and 2 will be turned

on. At that time, LNA1 and LNA2 and CW-SW circuits will

turn on, and the total CW output current coming from the

channel 1 and channel 2 trans-conductance amplifiers will

be differentially mixed into CW1+ and CW1-. The VDD cur-

rent is about 25mA increasing per CW channel. If setting

ADDR = 2 to 5 to CW mode ON state, all the LNA and CW

trans-conductance amplifiers are switched ON.

Anti-Aliasing Filter

The MD3872 provides two options for setting the AAF cor-

ner frequency in TGC mode. The first option is the sampling

frequency tracking method in which the corner frequency is

tracked with 1/3 of the sampling frequency. It is achieved by

the built-in six-bit resolution programmable RC value analog

anti-aliasing filter for tracking with sampling frequency, tem-

perature and process corner. It is enabled by CTL = 0 and

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