DM385 datasheet(72/280 Pages) TI1

72 / 280 page

DM385, DM388

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

www.ti.com

3.3.7

EMAC [(R)(G)MII Modes] and MDIO

3.3.7.1

EMAC

Table 3-18. EMAC Terminal Functions [(R)(G)MII]

SIGNAL NAME [1]

DESCRIPTION [2]

TYPE [3]

AAR BALL [4]

EMAC[0]_GMTCLK/EMAC[1]_RGRXC

GMII Source Asynchronous Transmit Clock / RGMII

I/O

AL6

Receive Clock

EMAC[0]_MCOL/EMAC[0]_RGRXCTL

[G]MII Collision Detect (Sense) input / RGMII Receive

AH1

Control

EMAC[0]_MCRS/EMAC[0]_RGRXD[2]

[G]MII Carrier Sense input / RGMII Receive Data

AH2

EMAC[0]_MRCLK/EMAC[0]_RGTXC

[G]MII Receive Clock / RGMII Transmit Clock

I/O

AK1

EMAC[0]_MRXDV/EMAC[1]_RGRXD[1]

[G]MII Receive Data Valid input / RGMII Receive Data

I/O

AJ6

EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0]

[G]MII Receive Data / RGMII Transmit Data

I/O

AK2

EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0]

[G]MII Receive Data / RGMII Receive Data

I/O

AL2

EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1]

[G]MII Receive Data / RGMII Receive Data

I/O

AL3

EMAC[0]_MRXD[3]/EMAC[1]_RGRXCTL

[G]MII Receive Data / RGMII Receive Control

I/O

AK3

EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3]

[G]MII Receive Data / RGMII Receive Data

I/O

AK4

EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3]

[G]MII Receive Data / RGMII Transmit Data

I/O

AJ4

EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2]

[G]MII Receive Data / RGMII Transmit Data

I/O

AL5

EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1]

[G]MII Receive Data / RGMII Transmit Data

I/O

AK5

EMAC[0]_MRXER/EMAC[0]_RGTXCTL

[G]MII Receive Data Error input / RGMII Transmit Enable

I/O

AJ2

EMAC[0]_MTCLK/EMAC[0]_RGRXC

[G]MII Transmit Clock input / RGMII Receive Clock

I/O

AG4

EMAC[0]_MTXD[0]/EMAC[1]_RGRXD[3]

[G]MII Transmit Data / RGMII Receive Data

I/O

AK6

EMAC[0]_MTXD[1]/EMAC[1]_RGTXD[1]

[G]MII Transmit Data / RGMII Transmit Data

I/O

AJ7

EMAC[0]_MTXD[2]/EMAC[1]_RGTXCTL

[G]MII Transmit Data / RGMII Trasmit Enable

I/O

AK7

EMAC[0]_MTXD[3]/EMAC[1]_RGTXD[0]

[G]MII Transmit Data / RGMII Transmit Data

I/O

AE4

EMAC[0]_MTXD[4]/EMAC[1]_RGTXD[2]

[G]MII Transmit Data / RGMII Transmit Data

I/O

AK8

EMAC[0]_MTXD[5]/EMAC[1]_RGTXC

[G]MII Transmit Data / RGMII Transmit Clock

I/O

AJ8

EMAC[0]_MTXD[6]/EMAC[1]_RGRXD[0]

[G]MII Transmit Data / RGMII Receive Data

I/O

AH8

EMAC[0]_MTXD[7]/EMAC[1]_RGTXD[3]

[G]MII Transmit Data / RGMII Transmit Data

I/O

AG8

EMAC[0]_MTXEN/EMAC[1]_RGRXD[2]

[G]MII Transmit Data Enable output / RGMII Receive

I/O

AF8

Data

EMAC[0]_RMCRSDV

RMII Carrier Sense input

AK1

EMAC[0]_RMRXD[0]

RMII Receive Data

AH1

EMAC[0]_RMRXD[1]

RMII Receive Data

AH2

EMAC[0]_RMRXER

RMII Receive Data Error input

AJ2

EMAC[0]_RMTXD[0]

RMII Transmit Data

AK2

EMAC[0]_RMTXD[1]

RMII Transmit Data

AL2

EMAC[0]_RMTXEN

RMII Transmit Data Enable output

AL3

EMAC[1]_GMTCLK

GMII Source Asynchronous Transmit Clock

EMAC[1]_MCOL

[G]MII Collision Detect (Sense) input

EMAC[1]_MCRS

[G]MII Carrier Sense input

EMAC[1]_MRCLK

[G]MII Receive Clock

EMAC[1]_MRXD[0]

[G]MII Receive Data

EMAC[1]_MRXD[1]

[G]MII Receive Data

EMAC[1]_MRXD[2]

[G]MII Receive Data

EMAC[1]_MRXD[3]

[G]MII Receive Data

EMAC[1]_MRXD[4]

[G]MII Receive Data

EMAC[1]_MRXD[5]

[G]MII Receive Data

EMAC[1]_MRXD[6]

[G]MII Receive Data

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