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MP8736 Datasheet(PDF) 15 Page - Monolithic Power Systems

Part # MP8736
Description  High Efficiency, Fast Transient, 6A, 19V Synchronous Buck Converter in a Tiny QFN20 (3x4mm) Package
PDF  23 Pages
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Manufacturer  MPS [Monolithic Power Systems]
Direct Link  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8736 Datasheet(HTML) 15 Page - Monolithic Power Systems

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MP8736– HIGHEFFICIENCY,FAST TRANSIENT,6A, 19V SYNCHRONOUSBUCKCONVERTERIN ATINY3X4mmPACKAGE
MP8736 Rev. 1.34
www.MonolithicPower.com
15
4/18/2012
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
Figure 7—Simplified Circuit in PWM Mode
with External Ramp Compensation
In PWM mode, an equivalent circuit with HS-FET
off
and
the
use
of
an
external
ramp
compensation circuit (R4, C4) is simplified in
Figure 7. The external ramp is derived from the
inductor ripple current. If one chooses C4, R9,
R1 and R2 to meet the following condition:
12
9
SW
4
1
2
RR
11
R
2F
C
5
R
R
⎛⎞
×
<×
+
⎜⎟
π×
×
+
⎝⎠
(5)
Where:
R4
C4
FB
C4
II +I
I
=≈
(6)
And the ramp on the VFB can then be estimated
as:
IN
O
12
RAMP
ON
44
1
2
9
VV
R//R
VT
RC
R // R
R
−
=×
×
×+
(7)
The downward slope of the VFB ripple then
follows
−
−
==
×
OUT
RAMP
SLOPE1
off
4
4
V
V
V
TR
C
(8)
As can be seen from equation 8, if there is
instability in PWM mode, we can reduce either
R4 or C4. If C4 can not be reduced further due to
limitation from equation 5, then we can only
reduce R4. For a stable PWM operation, the
Vslope1 should be design follow equation 9.
SW
ON
-3
ESR
OUT
slope1
O
OUT
SW
on
TT
+-R
C
Io 10
0.7 π
2
-V
V +
2L C
T -T
×
×
≥
××
(9)
Io is the load current.
In skip mode, the downward slope of the VFB
ripple is almost the same whether the external
ramp is used or not. Fig.9 shows the simplified
circuit of the skip mode when both the HS-FET
and LS-FET are off.
Figure 8—Simplified Circuit in skip Mode
The downward slope of the VFB ripple in skip
mode can be determined as follow:
()
REF
SLOPE2
12
OUT
V
V
(R
R // Ro) C
−
=
+×
(10)
Where Ro is the equivalent load resistor.
As described in Fig.6, VSLOPE2 in the skip mode is
lower than that is in the PWM mode, so it is
reasonable that the jitter in the skip mode is
larger. If one wants a system with less jitter
during ultra light load condition, the values of the
VFB resistors should not be too big, however, that
will decrease the light load efficiency.
Soft Start/Stop
The MP8736 employs soft start/stop (SS)
mechanism to ensure smooth output during
power-up and power shutdown. When the EN pin
becomes high, an internal current source (8.5μA)
charges up the SS CAP. The SS CAP voltage
takes over the REF voltage to the PWM
comparator. The output voltage smoothly ramps
up with the SS voltage. Once the SS voltage
reaches the same level as the REF voltage, it
keeps ramping up while VREF takes over the
PWM comparator. At this point, the soft start
finishes and it enters into steady state operation.
When the EN pin becomes low, the SS CAP
voltage is discharged through an 8.5uA internal
current source. Once the SS voltage reaches
REF voltage, it takes over the PWM comparator.
The output voltage will decrease smoothly with
SS voltage until zero level. The SS CAP value
can be determined as follows:
()
( )
( )
()
×μ
= SS
SS
SS
REF
Tms
I
A
CnF
VV
(11)
If the output capacitors have large capacitance
value, it’s not recommended to set the SS time



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