MP8736– HIGHEFFICIENCY,FAST TRANSIENT,6A, 19V SYNCHRONOUSBUCKCONVERTERIN ATINY3X4mmPACKAGE

MP8736 Rev. 1.34

www.MonolithicPower.com

17

4/18/2012

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© 2012 MPS. All Rights Reserved.

APPLICATION INFORMATION

Setting the Output Voltage-Large ESR Caps

For applications that electrolytic capacitor or POS

capacitor with a controlled output of ESR is set

as output capacitors. The output voltage is set by

feedback resistors R1 and R2. As figure 9 shows.

Figure 9—Simplified Circuit of POS Capacitor

First, choose a value for R2. R2 should be

chosen reasonably, a small R2 will lead to

considerable quiescent current loss while too

large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5kΩ-

50kΩ for R2, using a comparatively larger R2

when Vout is low, etc.,1.05V, and a smaller R2

when Vout is high. Then R1 is determined as

follow with the output ripple considered:

OUT

OUT

REF

12

REF

1

VV

V

2

RR

V

−Δ

−

=

(13)

OUT

V

Δ

is the output ripple determined by equation

22.

Setting the Output Voltage-Small ESR Caps

Figure10—Simplified Circuit of Ceramic

Capacitor

When low ESR ceramic capacitor is used in the

output, an external voltage ramp should be

added to FB through resistor R4 and capacitor

C4.The output voltage is influenced by ramp

in equation 7. R2 should be chosen reasonably,

a small R2 will lead to considerable quiescent

current loss while too large R2 makes the FB

noise sensitive. It is recommended to choose a

value

within

5kΩ-50kΩ

for

R2,

using

a

comparatively larger R2 when Vo is low,

etc.,1.05V, and a smaller R2 when Vo is high.

And the value of R1 then is determined as follow:

2

1

FB(AVG)

2

OUT

FB(AVG)

4

9

R

R=

V

R

-

(V

-V

) R +R

(14)

condition, etc., its value on the skip mode would

be lower than that of the PWM mode, which

means the load regulation is strictly related to the

regulation, a lower Vramp is suggested once it

meets equation 9.

deduced from equation 15.

12

FB(AVG)

REF

RAMP

12

9

R//R

1

VV

V

2R //R

R

=+

×

+

(15)

Usually, R9 is set to 0Ω, and it can also be set

following equation 16 for a better noise immunity.

It should also set to be 5 timers smaller than

R1//R2 to minimize its influence on Vramp.

9

4SW

1

R

2C

2F

≤

π×

×

(16)

Using equation 14 to calculate the output voltage

can be complicated. To simplify the calculation of

R1 in equation 14, a DC-blocking capacitor Cdc

can be added to filter the DC influence from R4

and R9. Figure 11 shows a simplified circuit with

external ramp compensation and a DC-blocking

capacitor. With this capacitor, R1 can easily be

obtained by using equation 17 for PWM mode

operation.

−−

=

+

OUT

REF

RAMP

12

REF

RAMP

1

(V

V

V

)

2

RR

1

VV

2

(17)

Cdc is suggested to be at least 10 times larger

than C4 for better DC blocking performance, and

should also not larger than 0.47uF considering

start up performance. In case one wants to use

larger Cdc for a better FB noise immunity,

combined with reduced R1 and R2 to limit the