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AM79C975VCW Datasheet(PDF) 101 Page - Advanced Micro Devices |
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AM79C975VCW Datasheet(HTML) 101 Page - Advanced Micro Devices |
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101 / 304 page  Am79C973/Am79C975 101 P R E L I M INARY Table 14. Am79C975 EEPROM Map Note: * Lowest EEPROM address. Word Addr. Byte Addr. Most Significant Byte Byte Addr. Least Significant Byte 00h* 01h 2nd byte of the ISO 8802-3 (IEEE/ANSI 802.3) station physical address for this node 00h First byte of the ISO 8802-3 (IEEE/ANSI 802.3) station physical address for this node, where “first byte” refers to the first byte to appear on the 802.3 medium 01h 03h 4th byte of the node address 02h 3rd byte of the node address 02h 05h 6th byte of the node address 04h 5th byte of the node address 03h 07h CSR116[15:8] (OnNow Misc. Config). 06h CSR116[7:0] (OnNow Misc. Config.) 04h 09h Hardware ID: must be 11h if compatibility to AMD drivers is desired 08h Reserved location: must be 00h 05h 0Bh User programmable space 0Ah User programmable space 06h 0Dh MSB of two-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh 0Ch LSB of two-byte checksum, which is the sum of bytes 00h-0Bh and bytes 0Eh and 0Fh 07h 0Fh Must be ASCII “W” (57h) if compatibility to AMD driver software is desired 0Eh Must be ASCII “W” (57h) if compatibility to AMD driver software is desired 08h 11h BCR2[15:8] (Miscellaneous Configuration) 10h BCR2[7:0] (Miscellaneous Configuration) 09h 13h BCR4[15:8] (Link Status LED) 12h BCR4[7:0] (Link Status LED) 0Ah 15h BCR5[15:8] (LED1 Status) 14h BCR5[7:0] (LED1 Status) 0Bh 17h BCR6[15:8] (LED2 Status) 16h BCR6[7:0] (LED2 Status) 0Ch 19h BCR7[15:8] (LED3 Status) 18h BCR7[7:0] (LED3 Status) 0Dh 1Bh BCR9[15:8] (Full-Duplex Control) 1Ah BCR9[7:0] (Full-Duplex Control) 0Eh 1Dh BCR18[15:8] (Burst and Bus Control) 1Ch BCR18[7:0] (Burst and Bus Control) 0Fh 1Fh BCR22[15:8] (PCI Latency) 1Eh BCR22[7:0] (PCI Latency) 10h 21h BCR23[15:8] (PCI Subsystem Vendor ID) 20h BCR23[7:0] (PCI Subsystem Vendor ID) 11h 23h BCR24[15:8] (PCI Subsystem ID) 22h BCR22[7:0] (PCI Subsystem ID) 12h 25h BCR25[15:8] (SRAM Size) 24h BCR25[7:0] (SRAM Size) 13h 27h BCR26[15:8] (SRAM Boundary) 26h BCR26[7:0] (SRAM Boundary) 14h 29h BCR27[15:8] (SRAM Interface Control) 28h BCR27[7:0] (SRAM Interface Control) 15h 2Bh BCR32[15:8] (MII Control and Status) 2Ah BCR32[7:0] (MII Control and Status) 16h 2Dh BCR33[15:8] (MII Address) 2Ch BCR33[7:0] (MII Address) 17h 2Fh BCR35[15:8] (PCI Vendor ID) 2Eh BCR35[7:0] (PCI Vendor ID) 18h 31h BCR36[15:8] (Conf. Sp. byte 43h alias) 30h BCR36[7:0] (Conf. Sp. byte 42h alias) 19h 33h BCR37[15:8] (DATA_SCALE alias0) 32h BCR37[7:0] (Conf. Sp. byte 47h0 alias) 1Ah 35h BCR38[15:8] (DATA_SCALE alias 1) 34h BCR38[7:0] (Conf. Sp. byte 47h1 alias) 1Bh 37h BCR39[15:8] (DATA_SCALE alias 2) 36h BCR39[7:0] (Conf. Sp. byte 47h2 alias) 1Ch 39h BCR40[15:8] (DATA_SCALE alias 3) 38h BCR40[7:0] (Conf. Sp. byte 47h3 alias) 1Dh 3Bh BCR41[15:8] (DATA_SCALE alias 4) 3Ah BCR41[7:0] (Conf. Sp. byte 47h4 alias) 1Eh 3Dh BCR42[15:8] (DATA_SCALE alias 5) 3Ch BCR42[7:0] (Conf. Sp. byte 47h5 alias) 1Fh 3Fh BCR43[15:8] (DATA_SCALE alias 6) 3Eh BCR43[7:0] (Conf. Sp. byte 47h6 alias) 20h 41h BCR44[15:8] (DATA_SCALE alias 7) 40h BCR44[7:0] (Conf. Sp. byte 47h7 alias) 21h 43h BCR48[15:8] N_IP_ADR[15:8] 42h BCR48[7:0] N_IP_ADR[7:0] 22h 45h BCR49[15:8] N_IP_ADR[31:24] 44h BCR49[7:0] N_IP_ADR[23:16] 23h 47h BCR50[15:8] M_IEEE_ADR[15:8] 46h BCR50[7:0] M_IEEE_ADR[7:0] 24h 49h BCR51[15:8] M_IEEE_ADR[31:24] 48h BCR51[7:0] M_IEEE_ADR[23:16] 25h 4Bh BCR52[15:8] M_IEEE_ADR[47:40] 4Ah BCR52[7:0] M_IEEE_ADR[39:32] 26h 4Dh BCR53[15:8] M_IP_ADR[15:8] 4Ch BCR53[7:0] M_IP_ADR[7:0] 27h 4Fh BCR54[15:8] M_IP_ADR[31:24] 4Eh BCR54[7:0] M_IP_ADR[23:16] 28h 51h Checksum adjust byte for the 82 bytes of the EEPROM contents, checksum of the 82 bytes of the EEPROM should total to FFh 50h BCR55[7:0] SMIU Slave Address 3Eh 7Dh Reserved for Boot ROM usage 7Ch Reserved for Boot ROM usage 3Fh 7Fh Reserved for Boot ROM usage 7Eh Reserved for Boot ROM usage |
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