AM79C975VCW datasheet(102/304 Pages) AMD

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102

Am79C973/Am79C975

P R E L I M INARY

The LED pins can be configured to operate in either

open-drain mode (active low) or in totem-pole mode

(active high). The output can be stretched to allow the

human eye to recognize even short events that last only

several microseconds. After H_RESET, the four LED

outputs are configured as shown in Table 15.

Table 15. LED Default Configuration

For each LED register, each of the status signals is

AND’d with its enable signal, and these signals are all

OR’d together to form a combined status signal. Each

LED pin combined status signal can be programmed to

run to a pulse stretcher, which consists of a 3-bit shift

each shift register is normally at logic 0. The OR gate

output for each LED register asynchronously sets all

three bits of its shift register when the output becomes

asserted. The inverted output of each shift register is

used to control an LED pin. Thus, the pulse stretcher

provides 2 to 3 clocks of stretched LED output, or 52

ms to 78 ms. See Figure 48.

Power Savings Mode

Power Management Support

The Am79C973/Am79C975 controller supports power

management as defined in the PCI Bus Power Man-

agement Interface Specification V1.1 and Network De-

vice Cla s s Po w e r Ma nage ment R e f e r e n c e

Specification V1.0.These specifications define the net-

work device power states, PCI power management in-

terface including the Capabilities Data Structure and

power management registers block definitions, power

management events, and OnNow network Wake-up

events. In addition, the Am79C973/Am79C975 control-

ler supports legacy power management schemes,

such as Remote Wake-Up (RWU) mode. When the

system is in RWU mode, PCI bus power is on, the PCI

clock may be slowed down or stopped, and the wake-

up output pin may drive the CPU's System Manage-

ment Interrupt (SMI) line.

Auxiliary Power

The Am79C973/Am79C975 uses the AUXDET pin to

detect whether it is powered by an auxiliary power sup-

ply that is always on or by the PCI power supply that

goes down during power saving modes.

If bit 15 of PMC is zero, indicating that PME assertion

in D3cold is not supported, the PME_Status and

PME_En bits of the PMCSR register will be reset by a

PCI bus reset (assertion of RST pin). This reset will ac-

tually occur after the EEPROM read following the reset

is complete to allow the controller to be configured.

To fully satisfy the requirements of the PCI power man-

agement specification in an adapter card configuration,

the AUXDET pin should be connected directly to the

auxiliary power supply and also to ground through a re-

sistor. This will sense the presence of the auxiliary

power and correctly report the capability of asserting

PME in D3cold.

For hardwired configurations where auxiliary power is

know to be always available or never available, the

AUXDET input may be disabled by connecting it di-

rectly or through a resistor to VDD. This will allow

BCR36 bit 15 to directly control PMC bit 15.

Figure 48. LED Control Logic

The general scheme for the Am79C973/Am79C975

power management is that when a PCI Wake-up event

is detected, a signal is generated to cause hardware

external to the Am79C973/Am79C975 device to put

the computer into the working (S0) mode.

The Am79C973/Am79C975 device supports three

types of wake-up events:

1. Magic Packet Detect

2. OnNow Pattern Match Detect

3. Link State Change

Figure 49 shows the relationship between these Wake-

up events and the various outputs used to signal to the

external hardware.

LED

Output

Indication

Driver Mode

Pulse Stretch

LED0

Link Status

Open Drain -

Active Low

Enabled

LED1

Receive

Status

Open Drain -

Active Low

Enabled

LED2

Open Drain -

Active Low

Enabled

LED3

Transmit

Status

Open Drain -

Active Low

Enabled

COL

COLE

FDLS

FDLSE

LNKS

LNKSE

RCV

RCVE

RCVM

RCVME

XMT

XMTE

Pulse

Stretcher

MR_SPEED_SEL

100E

MPS

MPSE

21510D-53

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