AM79C975VCW datasheet(105/304 Pages) AMD

105 / 304 page

Am79C973/Am79C975

105

P R E L I M INARY

Figure 50. Pattern Match RAM

Note: The setting of MPPLBA or EMPPLBA only ef-

fects the address detection of the Magic Packet frame.

The Magic Packet’s data sequence must be made up

of 16 consecutive copies of the device’s physical ad-

dress (PADR[47:0]), regardless of what kind of destina-

tion address it has.

T her e ar e tw o gene r a l met hods to place the

Am79C973/Am79C975 controller into the Magic

Packet mode. The first is the software method. In this

method, either the BIOS or other software, sets the

MPMODE bit (C SR5 , bit 1). The n Am 79 C973 /

Am79C975 controller must be put into suspend mode

(see description of CSR5, bit 0), allowing any current

network activity to finish. Finally, either PG must be

deasserted (hardware control) or MPEN (CSR5, bit 2)

must be set to 1 (software control).

Note: FASTSPNDE (CSR7, bit 15) has no meaning in

Magic Packet mode.

The second method is the hardware method. In this

method, the MPPEN bit (CSR116, bit 4) is set at power

up by the loading of the EEPROM. This bit can also be

set by software. The Am79C973/Am79C975 controller

will be placed in the Magic Packet Mode when either

the PG input is deasserted or the MPEN bit is set.

WUMI output will be asserted when the Am79C973/

Am79C975 controller is in the Magic Packet mode.

Magic Packet mode can be disabled at any time by as-

serting PG or clearing MPEN bit.

BCR 47

BCR 46

BCR 45

BCR Bit Number 15

0 15

PMR_B4

PMR_B3

PMR_B2

PMR_B1

PMR_B0

Pattern Match

RAM Address

Pattern Match RAM Bit Number

Comments

P3 pointer

P2 pointer

P1 pointer

P0 pointer

Pattern Enable

bits

First Address

P7 pointer

P6 pointer

P5 pointer

P4 pointer

Second

Address

Data Byte 3

Data Byte 2

Data Byte1

Data Byte 0

Pattern Control

Start Pattern

2+n

Data Byte 4n+3

Date Byte 4n+2

Data Byte 4n+1

Data Byte 4n+0

Pattern Control

End Pattern P1

Data Byte 3

Data Byte 2

Data Byte 1

Data Byte 0

Pattern Control

Start Pattern

J+m

Data Byte 4m+3 Data Byte 4m+2 Data Byte 4m+1 Data Byte 4m+0

Pattern Control

End Pattern Pk

Last Address

EOP

SKIP

MASK

21510D-55

AM79C975VCW Datasheet(PDF) 105 Page - Advanced Micro Devices

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