AM79C975VCW datasheet(109/304 Pages) AMD

109 / 304 page

Am79C973/Am79C975

109

P R E L I M INARY

I/O Resources

The Am79C973/Am79C975 controller requires 32

bytes of address space for access to all the various

internal registers as well as to some setup information

stored in an external serial EEPROM. A software reset

port is available, too.

The Am79C973/Am79C975 controller supports map-

ping the address space to both I/O and memory space.

The value in the PCI I/O Base Address register deter-

mines the start address of the I/O address space. The

tion utility

after system power-up. The PCI configura-

tion utility must also set the IOEN bit in the PCI

Command register to enable I/O accesses to the

Am79C973/Am79C975 controller. For memory mapped

I/O access, the PCI Memory Mapped I/O Base Address

The MEMEN bit in the PCI Command register must also

be set to enable the mode. Both base address registers

can be active at the same time.

The Am79C973/Am79C975 controller supports two

modes for accessing the I/O resources. For backwards

compatibility with AMD’s 16-bit Ethernet controllers,

Word I/O is the default mode after power up. The device

can be configured to DWord I/O mode by software.

I/O Registers

The Am79C973/Am79C975 controller registers are di-

vided into two groups. The Control and Status Regis-

ters (CSR) are used to configure the Ethernet MAC

engine and to obtain status information. The Bus Con-

trol Registers (BCR) are used to configure the bus in-

terface unit and the LEDs. Both sets of registers are

accessed using indirect addressing.

The CSR and BCR share a common Register Address

Port (RAP). There are, however, separate data ports.

The Register Data Port (RDP) is used to access a

CSR. The BCR Data Port (BDP) is used to access a

BCR.

In order to access a particular CSR location, the RAP

should first be written with the appropriate CSR ad-

dress. The RDP will then point to the selected CSR. A

read of the RDP will yield the selected CSR data. A

write to the RDP will write to the selected CSR. In order

to access a particular BCR location, the RAP should

first be written with the appropriate BCR address. The

BDP will then point to the selected BCR. A read of the

BDP will yield the selected BCR data. A write to the

BDP will write to the selected BCR.

Once the RAP has been written with a value, the RAP

value remains unchanged until another RAP write oc-

curs, or until an H_RESET or S_RESET occurs. RAP

is cleared to all 0s when an H_RESET or S_RESET oc-

curs. RAP is unaffected by setting the STOP bit.

Address PROM Space

The Am79C973/Am79C975 controller allows for con-

nection of a serial EEPROM. The first 16 bytes of the

EEPROM will be automatically loaded into the Address

PROM (APROM) space after H_RESET. Additionally,

the first six bytes of the EEPROM will be loaded into

CSR12 to CSR14. The Address PROM space is a con-

venient place to store the value of the 48-bit IEEE sta-

tion address. It can be overwritten by the host computer

and its content has no effect on the operation of the

controller. The software must copy the station address

from the Address PROM space to the initialization

block in order for the receiver to accept unicast frames

directed to this station.

The six bytes of the IEEE station address occupy the

first six locations of the Address PROM space. The

next six bytes are reserved. Bytes 12 and 13 should

match the value of the checksum of bytes 1 through 11

and 14 and 15. Bytes 14 and 15 should each be ASCII

“W” (57h). The above requirements must be met in

order to be compatible with AMD driver software.

APROMWE bit (BCR2, bit 8) must be set to 1 to enable

write access to the Address PROM space.

Reset Register

A read of the Reset register creates an internal soft-

ware reset (S_RESET) pulse in the Am79C973/

Am79C975 controller. The internal S_RESET pulse

that is generated by this access is different from both

the assertion of the hardware RST pin (H_RESET) and

from the assertion of the software STOP bit. Specifi-

cally, S_RESET is the equivalent of the assertion of the

RST pin (H_RESET) except that S_RESET has no ef-

fect on the BCR or PCI Configuration space locations.

The NE2100 LANCE-based family of Ethernet cards

requires that a write access to the Reset register fol-

lows each read access to the Reset register. The

Am79C973/Am79C975 controller does not have a sim-

ilar requirement. The write access is not required and

does not have any effect.

Note: The Am79C973/Am79C975 controller cannot

service any slave accesses for a very short time after a

read access of the Reset register, because the internal

S_RESET operation takes about 1 ms to finish. The

Am79C973/Am79C975 controller will terminate all

slave accesses with the assertion of DEVSEL and

STOP while TRDY is not asserted, signaling to the ini-

tiator to disconnect and retry the access at a later time.

Word I/O Mode

After H_RESET, the Am79C973/Am79C975 controller

is programmed to operate in Word I/O mode. DWIO

(BCR18, bit 7) will be cleared to 0. Table 20 shows how

the 32 bytes of address space are used in Word I/O

mode.

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