AM79C975VCW datasheet(107/304 Pages) AMD

107 / 304 page

Am79C973/Am79C975

107

P R E L I M INARY

There are four possible operation modes in the BSR

cell shown in Table 17.

Other Data Registers

Other data registers are the following:

1. Bypass Register (1 bit)

2. Device ID register (32 bits) (Table 18).

Note: The content of the Device ID register is the

same as the content of CSR88.

Reset

There are four different types of RESET operations that

may be performed on the Am79C973/Am79C975 de-

vice, H_RESET, S_RESET, STOP, and POR. The fol-

lowing is a description of each type of RESET

operation.

H_RESET

Hardware Reset (H_RESET) is an Am79C973/

Am79C975 reset operation that has been created by

the proper assertion of the RST pin of the Am79C973/

Am79C975 device while the PG pin is HIGH. When the

minimum pulse width timing as specified in the RST pin

description has been satisfied, then an internal reset

operation will be performed.

H_RESET will program most of the CSR and BCR reg-

isters to their default value. Note that there are several

CSR and BCR registers that are undefined after

H_RESET. See the sections on the individual registers

for details.

H_RESET will clear most of the registers in the PCI

configuration space. H_RESET will cause the micro-

code program to jump to its reset state. Following the

end of the H_RESET operation, the Am79C973/

Am79C975 controller will attempt to read the EEPROM

device through the EEPROM interface.

H_RESET will clear DWIO (BCR18, bit 7) and the

Am79C973/Am79C975 controller will be in 16-bit I/O

mode after the reset operation. A DWord write opera-

tion to the RDP (I/O offset 10h) must be performed to

set the device into 32-bit I/O mode.

S_RESET

Soft ware Re set (S_RESET) is an Am 79 C9 73 /

Am79C975 reset operation that has been created by a

read access to the Reset register, which is located at

offset 14h in Word

I/O mode or offset 18h in DWord

I/O mode from the Am79C973/Am79C975 I/O or mem-

ory mapped I/O base address.

S_RESET will reset all of or some portions of CSR0, 3,

4, 15, 80, 100, and 124 to default values. For the iden-

tity of individual CSRs and bit locations that are af-

fected by S_RESET, see the individual CSR register

descriptions. S_RESET will not affect any PCI configu-

ration space location. S_RESET will not affect any of

the BCR register values. S_RESET will cause the mi-

crocode program to jump to its reset state. Following

the end of the S_RESET operation, the Am79C973/

Am79C975 controller will not attempt to read the EE-

PROM device. After S_RESET, the host must perform

a full re-initialization of the Am79C973/Am79C975 con-

troller before starting network activity. S_RESET will

cause REQ to deassert immediately. STOP (CSR0, bit

2) or SPND (CSR5, bit 0) can be used to terminate any

pending bus mastership request in an orderly se-

quence.

S_RESET terminates all network activity abruptly. The

host can use the suspend mode (SPND, CSR5, bit 0)

to terminate all network activity in an orderly sequence

before issuing an S_RESET.

STOP

A STOP reset is generated by the assertion of the

STOP bit in CSR0. Writing a 1 to the STOP bit of CSR0,

when the stop bit currently has a value of 0, will initiate

a STOP reset. If the STOP bit is already a 1, then writ-

ing a 1 to the STOP bit will not generate a STOP reset.

STOP will reset all or some portions of CSR0, 3, and 4

to default values. For the identity of individual CSRs

and bit locations that are affected by STOP, see the in-

dividual CSR register descriptions. STOP will not affect

any of the BCR and PCI configuration space locations.

STOP will cause the microcode program to jump to its

reset state. Following the end of the STOP operation,

the Am79C973/Am79C975 controller will not attempt to

read the EEPROM device.

Note: STOP will not cause a deassertion of the REQ

signal, if it happens to be active at the time of the write

to CSR0. The Am79C973/Am79C975 controller will

wait until it gains bus ownership and it will first finish all

scheduled bus master accesses before the STOP reset

is executed.

Table 17. BSR Mode Of Operation

Capture

Shift

Update

System Function

Table 18. Device ID Register

Bits 31-28

Version

Bits 27-12

Part Number (0010 0110 0010 0101)

Bits 11-1

Manufacturer ID. The 11 bit manufacturer ID

cod for AMD is 00000000001 in accordance

with JEDEC publication 106-A.

Bit 0

Always a logic 1

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