AM79C975VCW datasheet(104/304 Pages) AMD

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104

Am79C973/Am79C975

P R E L I M INARY

the LCDET bit is set, the RWU pin will be asserted and

the PME_STATUS bit (PMCSR register, bit 15) will be

set. If either the PME_EN bit (PMCSR, bit 8) or the

PME_EN_OVR bit (CSR116, bit 10) are set, then the

PME will also be asserted.

OnNow Pattern Match Mode

In the OnNow Pattern Match Mode, the Am79C973/

Am79C975 device compares the incoming packets

with up to eight patterns stored in the Pattern Match

RAM (PMR). The stored patterns can be compared

with part or all of incoming packets, depending on the

pattern length and the way the PMR is programmed.

When a pattern match has been detected, then PMAT

bit (CSR116, bit 7) is set. The setting of the PMAT bit

causes the PME_STATUS bit (PMCSR, bit 15) to be

set, which in turn will asser t the PME pin if the

PME_EN bit (PMCSR, bit 8) is set.

Pattern Match RAM (PMR)

PMR is organized as an array of 64 words by 40 bits as

shown in Figure 50. The PMR is programmed indirectly

through the BCRs 45, 46, and 47. When the BCR45 is

written and the PMAT_MODE bit (BCR45, bit 7) is set

to 1, Pattern Match logic is enabled. No bus accesses

into the PMR are possible when the PMAT_MODE bit

is set, and BCR46, BCR47, and all other bits in BCR45

are ignored. When PMAT_MODE is set, a read of

BCR 45 r e tu r n s all bi ts u nde fin ed ex ce pt fo r

PMAT_MODE. In order to access the contents of the

PMR, PMAT_MODE bit should be programmed to 0.

When BCR45 is written to set the PMAT_MODE bit to

0, the Pattern Match logic is disabled and accesses to

the PMR are possible. Bits 6:0 of BCR45 specify the

address of the PMR word to be accessed. Writing to

BCR45 does not immediately affect the contents of the

PMR. Following the write to BCR45, the PMR word ad-

dressed by the bits 6:0 of the BCR45 may be read by

reading BCR45, BCR46, and BCR47 in any order. To

write to the PMR word, the write to BCR45 must be

followed by a write to BCR46 and a write to BCR47 in

that order to complete the operation. The PMR will not

actually be written until the write to BCR47 is complete.

The first two 40-bit words in this RAM serve as pointers

and contain enable bits for the eight possible match

patterns. The remainder of the RAM contains the

match patterns and associated match pattern control

bits. The byte 0 of the first word contains the Pattern

Enable bits. Any bit position set in this byte enables the

corresponding match pattern in the PMR, as an exam-

ple if the bit 3 is set, then the Pattern 3 is enabled for

matching. Bytes 1 to 4 in the first word are pointers to

the beginning of the patterns 0 to 3, and bytes 1 to 4 in

the second word are pointers to the beginning of the

patterns 4 to 7, respectively. Byte 0 of the second word

has no function associated with it. The byte 0 of the

words 2 to 63 is the Control Field of the PMR. Bit 7 of

this field is the End of Packet (EOP) bit. When this bit is

set, it indicates the end of a pattern in the PMR. Bits 6-

4 of the Control Field byte are the SKIP bits. The value

of the SKIP field indicates the number of the Dwords to

be skipped before the pattern in this PMR word is com-

pared with data from the incoming frame. A maximum

of seven Dwords may be skipped. Bits 3-0 of the Con-

trol Field byte are the MASK bits. These bits corre-

spond to the pattern match bytes 3-0 of the same PMR

word (PMR bytes 4-1). If bit n of this field is 0, then byte

n of the corresponding pattern word is ignored. If this

field is programmed to 3, then bytes 0 and 1 of the pat-

tern match field (bytes 2 and 1 of the word) are used

and bytes 3 and 2 are ignored in the pattern matching

operation.

The contents of the P M R are not affe c ted by

H_RESET, S_RESET, or STOP. The contents are un-

defined after a power up reset (POR).

Magic Packet Mode

In Magic Packet mode, the Am79C973/Am79C975

controller remains fully powered up (all VDD and VDDB

pins must remain at their supply levels). The device will

not generate any bus master transfers. No transmit op-

erations will be initiated on the network. The device will

continue to receive frames from the network, but all

frames will be automatically flushed from the receive

FIFO. Slave accesses to the Am79C973/Am79C975

controller are still possible. A Magic Packet is a frame

that is addressed to the Am79C973/Am79C975 con-

troller and contains a data sequence anywhere in its

data field made up of 16 consecutive copies of the de-

vice’s physical address (PADR[47:0]). The Am79C973/

Am79C975 controller will search incoming frames until

it finds a Magic Packet frame. It starts scanning for the

sequence after processing the length field of the frame.

The data sequence can begin anywhere in the data

field of the frame, but must be detected before the

Am79C973/Am79C975 controller reaches the frame’s

FCS field. Any deviation of the incoming frame’s data

sequence from the required physical address se-

quence, even by a single bit, will prevent the detection

of that frame as a Magic Packet frame.

The Am79C973/Am79C975 controller supports two dif-

ferent modes of address detection for a Magic Packet

frame. If MPPLBA (CSR5, bit 5) or EMPPLBA

(CSR116, bit 6) are at their default value of 0, the

Am79C973/Am79C975 controller will only detect a

Magic Packet frame if the destination address of the

packet matches the content of the physical address

the destination address of the Magic Packet frame can

be unicast, multicast, or broadcast.

AM79C975VCW Datasheet(PDF) 104 Page - Advanced Micro Devices

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