AM79C975VCW datasheet(151/304 Pages) AMD

151 / 304 page

Am79C973/Am79C975

151

P R E L I M INARY

ted, because no collision han-

dling is required in these modes.

Note that when the SRAM is be-

ing used, if the NOUFLO bit

(CSR80, bit 14) is set to 1, there

is the additional restriction that

the complete transmit frame must

be DMA’d into the Am79C973/

Am79C975 controller and reside

within a combination of the Bus

Transmit FIFO, the SRAM, and

the MAC Transmit FIFO.

When

the

SRAM

used,

SRAM_SIZE > 0, there is a re-

striction that the number of bytes

written is a combination of bytes

written into the Bus Transmit

FIFO and the MAC Transmit

FIFO.

The

Am79C973/

Am79C975 controller supports a

mode that will wait until a full

packet is available before com-

mencing with the transmission of

preamble. This mode is useful in

a system where high latencies

cannot be avoided. See Table 27.

Read/Write accessible only when

either the STOP or the SPND bit

is set. XMTSP is set to a value of

01b (64 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

Table 27. Transmit Start Point Programming

9-8

XMTFW[1:0] Transmit FIFO Watermark. XMT-

FW specifies the point at which

transmit

DMA

requested,

based upon the number of bytes

that could be written to the Trans-

mit FIFO without FIFO overflow.

Transmit DMA is requested at

any time when the number of

bytes specified by XMTFW could

be written to the FIFO without

causing Transmit FIFO overflow,

and the internal microcode en-

gine has reached a point where

the Transmit FIFO is checked to

determine if DMA servicing is re-

quired.

When operating in the NO-SRAM

mode

(no

SRAM

enabled),

SRAM_SIZE set to 0, the Bus

Transmit FIFO and the MAC

Transmit FIFO operate like a sin-

gle FIFO and the watermark val-

ue selected by XMTFW[1:0] sets

the number of FIFO byte loca-

tions that must be available in the

FIFO before receive DMA is re-

quested.

When operating with the SRAM,

the Bus Transmit FIFO and the

MAC Transmit FIFO operate in-

dependently on the bus side and

MAC side of the SRAM, respec-

tively. In this case, the watermark

value set by XMTFW[1:0] sets the

number of FIFO byte locations

that must be available in the Bus

Transmit FIFO. See Table 28.

Read/Write accessible only when

either the STOP or the SPND bit

is set. XMTFW is set to a value of

00b (16 bytes) after H_RESET or

S_RESET and is unaffected by

STOP.

7-0

DMATC[7:0] DMA Transfer Counter. Writing

and reading to this field has no ef-

fect.

Use

MAX_LAT

and

MIN_GNT in the PCI configura-

tion space.

XMTSP[1:0]

SRAM_SIZE

Bytes Written

128

220 max

128

Full Packet when

NOUFLO bit is set

Table 28. Transmit Watermark Programming

XMTFW[1:0]

Bytes Available

108

Reserved

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