AM79C975VCW datasheet(154/304 Pages) AMD

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154

Am79C973/Am79C975

P R E L I M INARY

setting of the MERRM bit (CSR3,

bit 11) and the IENA bit (CSR0,

bit 6).

The value in this register is inter-

preted as the unsigned number of

bus clock periods divided by two,

(i.e., the value in this register is

given in 0.1 ms increments.) For

example, the value 0600h (1536

decimal) will cause a MERR to be

indicated after 153.6 ms of bus

latency. A value of 0 will allow an

infinitely long bus latency, i.e.,

bus timeout error will never oc-

cur.

Read/Write accessible only when

either the STOP or the SPND bit

is set. This register is set to

0600h

H_RESET

S_RESET and is unaffected by

STOP.

CSR112: Missed Frame Count

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

MFC

Missed Frame Count. Indicates

the number of missed frames.

MFC will roll over to a count of 0

from the value 65535. The MFCO

bit of CSR4 (bit 8) will be set each

time that this occurs.

Read accessible always. MFC is

read only, write operations are ig-

nored.

MFC

cleared

H_RESET or S_RESET or by

setting the STOP bit.

CSR114: Receive Collision Count

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

RCC

Receive Collision Count. Indi-

cates the total number of colli-

sions

encountered

the

receiver since the last reset of the

counter.

RCC will roll over to a count of 0

from

the

value

65535.

The

RCVCCO bit of CSR4 (bit 5) will

be set each time that this occurs.

Read accessible always. RCC is

read only, write operations are ig-

nored.

RCC

cleared

H_RESET or S_RESET, or by

setting the STOP bit.

CSR116: OnNow Power Mode Register

Note: Bits 15-0 in this register are programmable

through the EEPROM.

Bit

Name

Description

31-14 RES

Reserved locations. Written as

zeros and read as undefined.

13 LCMODE_D3C. This bit is a read/write from the

PCI bus and is reset only at

power-on. This bit is not written

from the EEPROM. Power man-

agement software can set this bit

before going to D3cold and even

if there is a reset and the EE-

PROM loads because of an incor-

rect PG signal, the control bit will

not be changed. This bit is OR’ed

with LCMODE (CSR116 bit 8) for

OnNow link chnage, but not for

hardware link change

12 MPPEN_D3C

This bit is read/write from the the

PCI bus and is reset only at

power-on. This bit is not written

from the EEPROM. Power man-

agement software can set this bit

before going to D3cold and even

if there is a reset and the EE-

PROM loads because of an incor-

rect PG signal, the control bit will

not be changed. This bit is OR’ed

with MPPEN (CSR116 bit 4) for

both hardware magic packet or

OnNow magic packet.

11 PMAT_MODE_D3C

This bit is read/write from the the

PCI bus and is reset only at

power-on. This bit is not written

from the EEPROM. Power man-

agement software can set this bit

before going to D3cold and even

if there is a reset and the EE-

PROM loads because of an incor-

rect PG signal, the control bit will

not be changed. This bit is OR’ed

with PMAT_MODE (BCR45 bit 7)

for OnNow magic packet.

AM79C975VCW Datasheet(PDF) 154 Page - Advanced Micro Devices

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