AM79C975VCW datasheet(156/304 Pages) AMD

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156

Am79C973/Am79C975

P R E L I M INARY

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

RWU_POL

RWU Pin Polarity. If RWU_POL

is set to 1, the RWU pin is normal-

ly HIGH and asserts LOW; other-

wise RWU is normally LOW and

asserts HIGH.

Read/Write accessible only when

either the STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

RST_POL

PHY_RST Pin Polarity. If the

PHY_POL

set

the

PHY_RST pin is active LOW; oth-

erwise PHY_RST is active HIGH.

Read/Write accessible only when

either the STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

CSR122: Advanced Feature Control

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-1

RES

Reserved locations. Written as

zeros and read as undefined.

RCVALGN

Receive Packet Align. When set,

this bit forces the data field of ISO

8802-3 (IEEE/ANSI 802.3) pack-

ets to align to 0 MOD 4 address

boundaries (i.e., DWord aligned

addresses). It is important to note

that this feature will only function

correctly if all receive buffer

boundaries are DWord aligned

and all receive buffers have 0

MOD 4 lengths. In order to ac-

complish the data alignment, the

Am79C973/Am79C975 controller

simply inserts two bytes of ran-

dom data at the beginning of the

receive packet (i.e., before the

ISO 8802-3 (IEEE/ANSI 802.3)

destination address field). The

MCNT field reported to the re-

ceive descriptor will not include

the extra two bytes.

Read/Write accessible always.

RCVALGN

cleared

H_RESET or S_RESET and is

not affected by STOP.

CSR124: Test Register 1

This register is used to place the Am79C973/

Am79C975 controller into various test modes. The Runt

Packet Accept is the only user accessible test mode. All

other test modes are for AMD internal use only.

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-4

RES

Reserved locations. Written as

zeros and read as undefined.

RPA

Runt Packet Accept. This bit

forces

the

Am79C973/

Am79C975 controller to accept

runt packets (packets shorter

than 64 bytes).

Read accessible always; write

accessible only when STOP is

set to 1. RPA is cleared by

H_RESET or S_RESET and is

not affected by STOP.

2-0

RES

Reserved locations. Written as

zeros and read as undefined.

CSR125: MAC Enhanced Configuration Control

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-8

IPG

Inter Packet Gap. Changing IPG

allows the user to program the

Am79C973/Am79C975 controller

for aggressiveness on a network.

By changing the default value of

96 bit times (60h) the user can

adjust the fairness or aggressive-

ness

the

Am79C973/

Am79C975 MAC on the network.

By programming a lower number

of bit times other then the ISO/

IEC 8802-3 standard requires,

the Am79C973/Am79C975 MAC

will become more aggressive on

the network. This aggressive na-

ture

will

give

rise

the

Am79C973/Am79C975 controller

possibly “capturing the network”

at times by forcing other less ag-

AM79C975VCW Datasheet(PDF) 156 Page - Advanced Micro Devices

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