AM79C975VCW datasheet(152/304 Pages) AMD

152 / 304 page

152

Am79C973/Am79C975

P R E L I M INARY

CSR82: Transmit Descriptor Address Pointer

Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

TXDAPL

Contains the lower 16 bits of the

transmit descriptor address cor-

responding to the last buffer of

the previous transmit frame. If the

previous transmit frame did not

use buffer chaining, then TXDA-

PL contains the lower 16 bits of

the previous frame’s transmit de-

scriptor address.

When both the STOP or SPND

bits are cleared, this register is

updated

Am79C973/

Am79C975 controller immediate-

ly before a transmit descriptor

write.

Read accessible always. Write

accessible through the PXDAL

bits (CSR60) when the STOP or

SPND bit is set. TXDAPL is set to

0 by H_RESET and are unaffect-

ed by S_RESET or STOP.

CSR84: DMA Address Register Lower

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAL

This register contains the lower

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAL register is undefined

until

the

first

Am79C973/

Am79C975 controller DMA oper-

ation.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR85: DMA Address Register Upper

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-0

DMABAU

This register contains the upper

16 bits of the address of system

memory for the current DMA cy-

cle. The Bus Interface Unit con-

trols the Address Register by

issuing increment commands to

increment the memory address

for sequential operations. The

DMABAU register is undefined

until

the

first

Am79C973/

Am79C975 controller DMA oper-

ation.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR86: Buffer Byte Counter

Bit

Name

Description

31-16 RES

Reserved locations. Written as

zeros and read as undefined.

15-12 RES

Reserved. Read and written with

ones.

11-0

DMABC

DMA Byte Count Register. Con-

tains the two's complement of the

current size of the remaining

transmit

or receive

buffer in

bytes. This register is increment-

ed by the Bus Interface Unit. The

DMABC register is undefined un-

til written.

Read/Write accessible only when

either the STOP or the SPND bit

is set. These bits are unaffected

H_RESET,

S_RESET,

STOP.

CSR88: Chip ID Register Lower

Bit

Name

Description

31-28 VER

Version. This 4-bit pattern is

silicon-revision dependent.

Read accessible only when either

the STOP or the SPND bit is set.

AM79C975VCW Datasheet(PDF) 152 Page - Advanced Micro Devices

AM79C975VCW Datasheet(HTML) 152 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL