AM79C975VCW datasheet(155/304 Pages) AMD

155 / 304 page

Am79C973/Am79C975

155

P R E L I M INARY

10 PME_EN_OVR PME_EN Overwrite. When this

bit is set and the MPMAT or

LCDET bit is set, the PME pin will

always be asserted regardless of

the state of PME_EN bit.

Read/Write accessible only when

either the STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

LCDET

Link Change Detected. This bit is

set when the MII auto-polling log-

ic detects a change in link status

and the LCMODE bit is set.

LCDET is cleared when power is

initially applied (POR).

Read/Write accessible always.

LCMODE

Link Change Wake-up Mode.

When this bit is set to 1, the

LCDET bit gets set when the MII

auto polling logic detects a Link

Change.

Read/Write accessible only when

either the STOP bit or the SPND

bit is set. Cleared by H_RESET

and is not affected by S_RESET

or setting the STOP bit.

PMAT

Pattern Matched. This bit is set

when the PMMODE bit is set and

an OnNow pattern match occurs.

PMAT is cleared when power is

initially applied (POR).

Read accessible always.

EMPPLBA

Magic Packet Physical Logical

Broadcast Accept. If both EMP-

PLBA and MPPLBA (CSR5, bit 5)

are at their default value of 0, the

Am79C973/Am79C975 controller

will only detect a Magic Packet

frame if the destination address

of the packet matches the con-

tent of the physical address regis-

ter (PADR). If either EMPPLBA or

MPPLBA is set to 1, the destina-

tion address of the Magic Packet

frame can be unicast, multicast,

or broadcast. Note that the set-

ting of EMPPLBA and MPPLBA

only affects the address detection

of the Magic Packet frame. The

Magic Packet frame’s data se-

quence must be made up of 16

consecutive physical addresses

(PADR[47:0]) regardless of what

kind of destination address it has.

Read/Write accessible always.

EMPPLBA

set

H_RESET or S_RESET and is

not affected by setting the STOP

bit.

MPMAT

Magic Packet Match. This bit is

set when PCnet-FAST+ detects a

Magic Packet while it is in the

Magic Packet mode.

MPMAT is cleared when power is

initially applied (POR).

Read/Write accessible always.

MPPEN

Magic Packet Pin Enable. When

this bit is set, the device enters

the Magic Packet mode when the

PG input goes LOW or MPEN bit

(CSR5, bit 2) gets set to 1. This

bit is OR’ed with MPEN bit

(CSR5, bit 2).

Read/Write is accessible only

when either the STOP bit or the

SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

RWU_DRIVER

RWU Driver Type. If this bit is set

to 1, RWU is a totem pole driver;

otherwise RWU is an open drain

output.

Read/Write is accessible only

when either the STOP bit or the

SPND bit is set. Cleared by

H_RESET and is not affected by

S_RESET or setting the STOP

bit.

RWU_GATE

RWU Gate Control. If this bit is

set, RWU is forced to the high Im-

pedance State when PG is LOW,

regardless of the state of the MP-

MAT and LCDET bits.

Read/Write accessible only when

either the STOP bit or the SPND

AM79C975VCW Datasheet(PDF) 155 Page - Advanced Micro Devices

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