AM79C983A datasheet(32/60 Pages) AMD

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Am79C983A

PRELIMINARY

MX3-X0

Transceiver

QuIET Device ID

1 to 15

Reserved

Repeater Device and Revision Register

Address:

1111 1100

This is a read only register. The 8-bit quantity read has

the following format:

Device Type. These bits contain the IMR2

device code.

D3-0

0010

IMR2

Revision Number. These bits contain the revision

number. Software may interrogate these bits to de-

termine additional features that may be available

with future versions of the device.

V3-0 0000

Revision 0

Device Conﬁguration

Address:

1111 1101

This is a read/write register. When this register is writ-

ten, zeros must be written into unassigned ﬁelds. The

8-bit quantity has the following format:

Repeater Reset. Setting Bit R resets the registers,

repeater, and MAC engine. It is the functional

equivalent of hardware reset, with the exception

that the microprocessor interface is not reset and

the ability to access RMON and port attribute reg-

isters is maintained.

Management Reset. Setting this bit causes the

MAC engine to be reset. When the M bit is set, the

IMR2 device still functions as a repeater, however

MIB tracking is disabled. Setting this bit also allows

the RMON registers and the attribute registers to

be preset by software.

This bit conﬁgures the RAUI port. The conﬁgura-

tion options are:

Normal Mode. The RAUI port is conﬁgured

as a standard AUI port.

Reverse Mode. RCI is an output, i.e., RCI

generates a 10-MHz signal during a collision.

When a bit on an interrupt register is set, the interrupt

bit on the Status Register is set and the INT pin is

driven. These registers are accessed by writing the bit

pattern 0000 0001 to the C Register. These registers

are read only and are cleared to 0 upon reading. When

all the interrupt registers are clear (all bits zero), the In-

terrupt bit of the Status Register and INT are cleared.

Note that for each interrupt register there is a corre-

sponding interrupt enable register. The bits on the inter-

rupt register cannot set unless the corresponding bits

on the corresponding interrupt enable register are set.

Port Partition Status Change Interrupt

Address:

1110 0000

Any port changing state between partitioned and re-

connected causes the appropriate register bit to be set

to 1.

The format is as follows:

Pn/AUI/RAUI

Partition status of corresponding

port unchanged

Partition status of corresponding

port changed

Runts with Good FCS Interrupt

Address:

1110 0001

Any port receiving a packet that is less than 64 octets

(not including preamble and SFD), but is otherwise well

formed and error free, causes the appropriate bit to be

set. The format is as follows:

Pn/AUI/RAUI/EP

No runts with valid FCS

Runt with valid FCS

Link Status Change Interrupt

Address:

1110 0010

A change in the Link Test state of a twisted pair port

associated with a repeater port (from fail to pass or pass

to fail) causes the appropriate bit to be set in this register.

This register is only valid when a QuIET device is

connected to the corresponding port(s).

D Port Read

MSB

LSB

D Port Read/Write

MSB

LSB

RAUI

AUI P11 P10 P9

D Port Read

Byte 0

Byte 1

LSB

MSB

RAUI

AUI P11 P10 P9

D Port Read

Byte 0

Byte 1

MSB

LSB

TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0

SP3 SP2 SP1 SP0 TP11 TP10 TP9 TP8

Byte 0

Byte 1

D Port Read

LSB

MSB

AM79C983A Datasheet(PDF) 32 Page - Advanced Micro Devices

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