AM79C983A datasheet(41/60 Pages) AMD

41 / 60 page

Am79C983A

PRELIMINARY

the register jumps to the next level automatically.The data

format is as follows:

Packet

0 - Empty

1 - Valid

N3-0

Port Number

Very Long Event

DRE

Data Rate Error

RNT

Runt Packet

Short Event

Long Event

Alignment Error

FCS

FCS Error

Bytes 2-7

Source Address. It is read low

order byte to high order byte.

Note: The FIFO is emptied by reading. If the FIFO is

full, nothing more is recorded in Sample Error Status. If

the FIFO is empty (bit E = 0), there is nothing in the re-

maining 7 bytes; therefore, the next access will be the

ﬁrst byte of the 8-byte register.

Report Packet Size

Address:

1110 0011

Report Packet Size is a two-byte register. The eleven

least signiﬁcant bits are used. It sets the length of the

original packet (in octets) that is transmitted over the

Packet Report Port. The LS Byte is accessed ﬁrst. The

limits are 14 bytes (binary 000000001110) and 1535

bytes (binary 10111111111). If the register is set at

less than 14, 14 bytes of the original packet are trans-

mitted over the Packet Reports Port. If the register is

set at greater than 1535 bytes, all of the original packet

is sent over the Packet Report Port.

STATS Control

Address:

1110 0100

STATS Control is a 1-byte register. It sets the operation

of the Packet Report Port and the RAUI port.

0 Packet tagging is disabled

1 Packet tagging is enabled

0 Appending of a new FCS during port tag-

ging is disabled

1 Appending of a new FCS during port tag-

ging is enabled

Registers

Port Attribute registers are accessed by writing the ap-

propriate port number into the C register, followed by

the attribute number. The table below shows the corre-

sponding register bank for each port.

Except for the Last Source Address Register and the

Preferred Source Register, all registers are four bytes

long and read only unless special conditions are met.

The Last Source Address Register and the Preferred

Source Address Register are six bytes long and their

contents can be written and read.

Once the C Register is programmed with a valid port

and attribute number, the corresponding attribute is

transferred to a holding register upon reading the ﬁrst

byte. Subsequent accesses to the D register access

the value in a least signiﬁcant to most signiﬁcant byte

order. During a read, once the last byte is read, the at-

tribute value is re-transferred to the holding register

and the sequence can be restarted.

When writing the Last Source Address Register and the

Preferred Source Register, if the sequence is aborted

prior to the 6th consecutive write cycle, the register value

is not altered. The sequence (read or write) may be

aborted and restarted by programming the C register.

DRE

RNT S

FCS

bit 23

bit 16

bit 56

D Port Read/Write

Byte 0

Byte 1

MSB

LSB

Byte 2

Byte 3

Byte 4

Byte 5

Byte 6

Byte 7 bit 63

bit 0

bit 15

bit 8

D Port Read/Write

LSB

Byte 0

Byte 1

bit 7

MSB

D Port Read/Write

MSB

LSB

Port

0001 0000

0001 0001

0001 0010

0001 0011

0001 0100

0001 0101

0001 0110

0001 0111

0001 1000

0001 1001

0001 1010

0001 1011

0001 1100

AUI

0001 1101

RAUI

0001 1110

Expansion Bus

(activity recorded

when MACEN

is TRUE)

AM79C983A Datasheet(PDF) 41 Page - Advanced Micro Devices

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